Hardware Components
UG0048 User Guide Revision 5.1
6
board, the red LED D19 illuminates to indicate that an external supply is connected to the board. As soon
as switch SW11 is moved to the ON position (to the right, as labeled on the board OFF/ON), the disabling
ground signal is removed from pin 7 of U11 and the regulator begins to provide power at its output.
The U11 switching voltage regulator provides a dedicated 3.3 V supply at its output. The board’s 3.3 V
supply is used for feeding separate regulators that deliver 1.5 V (through U15), 1.8 V (through U12), and
2.5 V (through U15). The 1.5 V is required for the core voltage of the ProASIC3/E family, and the 2.5 V is
required for demonstrating LVDS extended I/O bank capability.
The presence of these voltages is indicated by four green LEDs (D13, D9, D10, and D11) illuminating at
the top right of the board. Each LED is labeled with the voltage it represents and its component identifier.
All four voltages are selectable on the I/O banks 4 and 5 (the two southernmost banks) of a ProASIC3E
device using SW9 and SW8 switches respectively.
Note:
Only ProASIC3E devices have eight I/O banks. ProASIC3 devices have four I/O banks—one per side of
the PQ208 package. If a ProASIC3 device is placed in the socket, then both SW8 and SW9 should be set
at same voltage level to power I/O bank 2.
The 3.3 V supply is also used for optionally providing the VPUMP programming voltage. This VPUMP
voltage may be provided to the chip during programming by applying a FlashPro4 programmer to the J1
interface and selecting VPUMP from the FlashPro v9.1 (or later) programming software. VPUMP voltage
may also be provided directly to the chip from the board.
Leave the JP48 jumper in place to apply 3.3 V supply to the VPUMP pin (106 of the PQ208 packaged
FPGA).
Note:
If both FlashPro4 or latest and the board are selected to provide VPUMP
,
then it is the connection on the
board that will override, as FlashPro4 will detect that a voltage is available, issue an information
message in the programming software, and then move the VPUMP output pin to a tristate value, allowing
the board to provide all the power.
The board must be powered-up during programming because the chip needs its core voltages to be
provided and VJTAG must be detected by the FlashPro4 programmer in order for it to set its JTAG signal
voltages to the right level.
The OLED device requires low current 10 V supply and 3.3 V supply to operate correctly. These voltages
are provided by LT1615 and LM2678S modules, as shown in
The ex9 V power supply is rated at 2 A maximum. On the first of the full-page dedicated
schematics shown in the
page 26, note that the 3.3 V supply is rated at 5 A
maximum. The derived power supplies of 1.5 V, 1.8 V, and 2.5 V are rated at 2 A max each, and the
OLED 10 V power supply is rated at 100 mA, as shown in
page 35. Clearly, not all these
derived supplies can be working at their respective maximum current outputs simultaneously. The
maximum ratings are for the individual regulator ICs and cannot be numerically added together.
The U11 (LM2678S-3.3) component is rated for an input voltage range of +8 V to +40 V, so a wide range
of power supplies may be used with the board with no concern about over-voltage conditions occurring
from inadvertent accidental usage of the wrong power supply. However, the user must ensure that the
voltage provided is positive at the center pin of the J18 connector and grounded on the outside. Greater
heating of the regulator chips can be observed with higher voltages. It is recommended that only the
included power supply or an equivalent substitute be used with the Starter Kit. The included power
supply has been rated for this board, including Microsemi SoC Products Group Daughter Cards that may
be attached to the board.
3.4.1
Power Supply Connections of Daughter Card
Limited power is supplied to a daughter card by the board. The connector for the daughter card is shown
in
page 32 and is the J12 header. All the FPGA voltages 1.5 V, 1.8 V, 2.5 V, and 3.3 V are
provided to the daughter card through a 12-pin 0.1 inch pitch connector. The voltages are arranged with
a no-connection pin interspersing the voltage pins. This prevents accidental use of a jumper to short a
supply rail to ground, which could connect differing supply rails together.
The purpose is not to protect the power supply regulators, as these will go high-impedance when an
over-voltage condition is detected. It is to protect the FPGA from unintentional application of a higher
