Microsemi ProASIC3/E Proto Kit User Manual Download Page 38

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Appendix: Board Schematics

UG0048 User Guide Revision 5.1

Figure 13 •

FPGA Headers and Expansion Bus

IO127PDB7V1

IO127NDB7V1

IO126PDB7V0

IO126NDB7V0

GEC1/IO104PDB6V0

GEC0/IO104NDB6V0

IO106PDB6V0

IO106NDB6V0

GAA2/IO134PDB7V1

IO122PPB7V0

IO124PSB7V0

IO122NPB7V0

GEA1/IO102PPB6V0

GAB2/IO133PSB7V1

IO134NDB7V1

GEB0/IO102NPB6V0

IO121PSB7V0

GFA1/IO118PPB6V1

CLOCKF

GFC1/IO120PSB7V0

IO108NPSB6V0

GEB0/IO103NPB6V0

GEB1/IO103PPB6V0

VMV5

IO100PDB5V2

IO101NDB5V2

IO98PSB5V2

IO92NDB5V1

IO96PSB5V2

IO99NDB5V2

IO88NDB5V0

IO85PPB5V0

IO85NPB5V0

IO83PPB5V0

IO78NPB4V1

IO80PDB4V1

IO83NPB5V0

IO78PPB4V1

IO72PDB4V0

IO76PDB4V1

GDB2/IO69PSB4V0

TMS

TCK

GDC2/IO70PDB4V0

GEA2/IO101PDB5V2

GEC2/IO99PDB5V2

GEB2/IO100PDB5V2

IO94PDB5V1

IO88PDB5V0

IO92PDB5V1

IO94NDB5V1

IO84NPB5V0

IO82NPB5V0

IO84PPB5V0

IO80NDB4V1

IO79PPB4V1

IO79NPB4V1

IO82PPB5V0

IO76NDB4V1

IO70NDB4V0

IO72NDB4V0

GDA2/IO68PDB4V0

VMV4

TDI

IO68NDB4V0

VMV3

GDB1/IO66PPB3V1

GDB0/IO66NPB3V1

IO62PDB3V1

GCB2/IO54PSB3V0

IO58PDB3V0

GDC1/IO65PDB3V1

GCA1/IO52PPB3V0

IO49NDB2V1

IO47NDB2V1

IO48PSB2V1

GCB1/IO51PDB2V1

IO53NDB3V0

IO43NDB2V0

GBC2/IO38PSB2V0

IO40NDB2V0

GBB2/IO37PSB2V0

IO44NDB2V1

TRSTB

TDO

GDA0/IO67NPB3V1

VJTAG

GDC0/IO65NDB3V1

IO58NDB3V0

IO62NDB3V1

GDA1/IO67PPB3V1

GCA2/IO53PDB3V0

GCB0/IO51NDB2V1

CLOCKC

IO49PDB2V1

IO44PDB2V1

IO47PDB2V1

GCC1/IO50PSB2V1

GCC2/IO55PSB3V0

IO40PDB2V0

VMV2

GBA2/IO36PSB2V0

IO43PDB2V0

GBA1/IO35PDB1V1

GBB1/IO34PDB1V1

GBA0/IO35NDB1V1

GBC1/IO33PDB1V1

IO31PDB1V1

GBC0/IO33NDB1V1

GBB0/IO34NDB1V1

IO27PDB1V0

IO23PPB1V0

IO27NDB1V0

IO23NPB1V0

IO21NDB1V0

IO21PDB1V0

IO22PSB1V0

IO31NDB1V1

IO18PPB0V2

IO18NPB0V2

IO19NPB0V2

IO17PPB0V2

IO19PPB0V2

VMV1

IO17NPB0V2

IO15PDB0V2

IO16NPB0V2

IO11PSB0V1

IO13NDB0V2

IO15NDB0V2

IO09NDB0V1

IO07NDB0V1

IO07PDB0V1

IO05NDB0V0

GAC0/IO02NDB0V0

GAC1/IO02PDB0V0

IO05PDB0V0

IO09PDB0V1

GAB0/IO01NDB0V0

GAA0/IO00NDB0V0

GAA1/IO00PDB0V0

GAB1/IO01PDB0V0

IO16PPB0V2

VMV0

T1+

T2+

T2-

IO127PDB7V1

IO127NDB7V1

IO126PDB7V0

IO126NDB7V0

T3+

T4+

T4-

IO106PDB6V0

IO106NDB6V0

GEC1/IO104PDB6V0

GEC0/IO104NDB6V0

VMV1

VMV2

VMV3

VMV6

VMV7

VMV0

T1-

T3-

GFB1/IO119PDB7V0

GFB0/IO119NDB7V0

GFC2/IO115PPB6V1

IO115NPB6V1

GFB2/IO116PPB6V1

IO116NPB6V1

VPUMP

VMV5

VMV7

VMV6

RX1+

RX1-

RX2+

RX2-

RX3+

RX3-

RX4+

RX4-

VMV4

1.5V

2.5V

1.5V

1.8V

3.3V

2.5V

3.3V

1.5V

1.8V

2.5V

3.3V

1.5V

1.8V

2.5V

3.3V

Microsemi

Approvals:

Eng Mgr:

Engr:

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Assembly

Date:

Title:

Size:

ocument No:

DRAWN BY:

Rev

BALA

Microsemi

Approvals:

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Engr:

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Assembly

Date:

Title:

Size:

ocument No:

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Rev

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Microsemi

Approvals:

Eng Mgr:

Engr:

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ocument No:

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SCHEMATIC DIAGRAM NOTES

1.UNLESS STATED OTHERWISE:

A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE.

B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE.

BOARD INFORMATION

PCB FAB:,REV.02 PCB ASSEMBLY:,REV.02

FPGA Headers & Expansion Bus

04/27/11

NOTE:- 1) PLACE RESISTORS R49,50,51,52 CLOSE TO A3P PART(U8)(PAGE 3) IN LAYOUT

A3PE STARTER KIT BOARD REV.A

Power Connector for Daughter Board

2) ALL RXn+ AND RXn- (n=0,1,2,3,4) TRACE PAIRS SHOULD BE MAINTAINED

EQUIDISTANT FROM THE FPGA TO THE TERMINATING RESISTORS.

3) ALL RXn+ AND RXn- (n=0,1,2,3,4)TRACE PAIRS TO BE

100 OHM IMPEDANCE CONTORLLED

(U8 PIN 11)

(U8 PIN 12)

(U8 PIN 13)

(U8 PIN 14)

(U8 PIN 42)

(U8 PIN 43)

(U8 PIN 44)

(U8 PIN 45)

DVP-100-000300-001

JP48JP48

J14C

HEADER 2X52

J14C

HEADER 2X52

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

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131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

R52

100 / 1%

R52

100 / 1%

J14B

HEADER 2X52

J14B

HEADER 2X52

100

101

102

103

104

J14A

HEADER 2X52

J14A

HEADER 2X52

R50

100 / 1%

R50

100 / 1%

J14D

HEADER 2X52

J14D

HEADER 2X52

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

R51

100 / 1%

R51

100 / 1%

J12

HEADER 2X6

J12

HEADER 2X6

SW9SW9

SW8SW8

R49

100 / 1%

R49

100 / 1%

Summary of Contents for ProASIC3/E Proto Kit

Page 1: ...UG0048 User Guide ProASIC3 E Starter Kit ...

Page 2: ...e suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or ...

Page 3: ...e Programming the Design 8 3 5 3 Jumpers for Isolating Switches and LEDs from FPGA 9 3 6 Clock Circuits 10 3 6 1 40 MHz Oscillator 10 3 7 LED Device Connections 10 3 8 Switches Device Connections 11 3 9 LVDS Channels 11 4 Setup and Self Test 14 4 1 Software Installation 14 4 2 Hardware Installation 14 4 3 Testing the Starter Kit Board 14 4 4 Programming the Test File 14 5 Description of Test Desig...

Page 4: ...UG0048 User Guide Revision 5 1 iv 8 1 I O Naming Conventions 22 8 2 208 Pin PQFP 23 9 Appendix Board Schematics 26 9 1 Top Level View 27 9 2 ProASIC3 E Starter Kit Board Schematics 29 ...

Page 5: ...on at 300 Mbps 18 Figure 7 208 Pin PQFP 23 Figure 8 Top Level View of ProASIC3 E Starter Kit Board 27 Figure 9 Bottom Level View of ProASIC3 E Starter Kit Board 28 Figure 10 Bottom Level View of ProASIC3 E Starter Kit Board 29 Figure 11 ProASIC3 FPGA 30 Figure 12 Push Button and Hex Switches 31 Figure 13 FPGA Headers and Expansion Bus 32 Figure 14 Clocks Oscillators and Reset 33 Figure 15 Decoupli...

Page 6: ...of Jumpers 9 Table 3 LED Device Connections 11 Table 4 Switch Device Connections 11 Table 5 Color Convention on CAT 5E Primary 12 Table 6 Color Convention on CAT 5E Secondary 12 Table 7 FPGA LVDS I O Pin Details 13 Table 8 Switches 16 Table 9 Device Connections for 208 Pin PQFP 24 ...

Page 7: ...oard image are updated 1 2 Revision 5 0 The following was a summary of the changes in revision 5 0 of this document The part number for the ProASIC3 E Starter Kit was changed from A3PE STARTER KIT to A3PE STARTER KIT 2 SAR 42164 In the FPGA OLED Interface section PMO13701 was corrected to PMO18701 SAR 42164 1 3 Revision 4 0 Libero IDE software has been updated to Libero SoC throughout the document...

Page 8: ...oASIC3 E Starter Kit and lists the power supply and software system requirements 2 1 Kit Contents The following table lists the contents of the ProASIC3 E Starter Kit Table 1 Kit Contents Item Quantity ProsASIC3 E Starter Kit Board with an A3PE1500 PQG208 1 FlashPro4 programmer 1 9 V power supply with international adapters 1 Quickstart card 1 ...

Page 9: ...3 3 V I O voltages on banks 4 and 5 southern side 10 pin 0 1 inch pitch programming connector compatible with Altera connections 40 MHz oscillator and two independent manual clock options for global reset and pulse Eight LEDs driven by outputs from the device Jumpers allow disconnection of all external circuitry from the FPGA Two mono stable pulse generator switches global and reset Four switches ...

Page 10: ...fpga proasic3 e documents A block diagram of the ProASIC3 E Starter kit board is shown in the following figure and will facilitate understanding of the more detailed schematics shown in the Appendix Board Schematics page 26 Figure 1 ProASIC3 E Starter Kit Board Top Level View Full schematics are available for download from the Microsemi SoC Products Group website The electronic versions of the ded...

Page 11: ...E and ProASIC3 devices 2 To demonstrate the lowest possible power consumption for the part Perpetually powering the PLL lines would not achieve that 3 It is easy to place a jumper on the appropriate jumper header when desired 3 4 Power Supply A 9 V power supply is provided with the kit as shown in the following figure There are many power supply components in the starter kit board to illustrate th...

Page 12: ... the chip needs its core voltages to be provided and VJTAG must be detected by the FlashPro4 programmer in order for it to set its JTAG signal voltages to the right level The OLED device requires low current 10 V supply and 3 3 V supply to operate correctly These voltages are provided by LT1615 and LM2678S modules as shown in Figure 16 page 35 The external 9 V power supply is rated at 2 A maximum ...

Page 13: ...ts are RoHS compliant Schematics for Rev3 and Rev2 boards are the same when viewed as PDF files but there is a short in the board layers on the Rev2 that has been corrected for Rev3 The rare Rev1 prototype boards had different schematics and are not discussed in this document 3 4 2 1 Procedure for Rev A Boards To determine if the board is a Starter Kit Rev A board A Rev A board is recognized by ex...

Page 14: ...ny device in the ProASIC3 E family in the PQ208 package can be placed into the socket In a kit with a socket on the board a reasonable number of insertions may be made if the user exercises great care in inserting components into the socket Note Screw down sockets are not clam shell sockets and do have a lifetime of about 20 insertions although far greater may be achieved with careful placement an...

Page 15: ...ocated on the bottom right of the board They are labeled with Bit0 Bit1 Bit2 and Bit3 on the silk screen as well as being labeled with the I O pin on the FPGA to which each is connected This allows individually control the desired effect of a switch and by connecting directly to the FPGA side of a disconnected jumper hold a particular pin at a chosen logic level while continuing to use the hex swi...

Page 16: ...ing pads This area is used to solder a TQ100 part and then connect that part by adding discrete wires to the pads and connecting it to desired pins on the board The main purpose of this is to allow a previously programmed TQ100 packaged device to be used to provide a more interesting system application 3 5 3 3 Layering on Board The complete board design and manufacturing files are available at htt...

Page 17: ...e in place the device I O can be driven by the switches listed in the following table Pressing a switch drives a 1 into the device The 1 continues to drive while the switch is in place Releasing a switch drives a zero into the device To use the device I O for other purposes remove the jumpers 3 9 LVDS Channels Four LVDS channels with up to a maximum signaling rate of 350 MHz are supported on the S...

Page 18: ...lowing table using the following color convention on the second LVDS connector referred to as l CAT 5E SECONDARY for the purpose of differentiation Note The colors refer to the colors that will appear on the CAT 5E cable The pin numbers correspond to the pin numbers of an RJ 45 connector Note that the CAT 5E PRIMARY connections are labeled for the purposes of what is regarded as standard connectio...

Page 19: ...J40 RJ45 connector is referred as CAT 5E PRIMARY connector 3 J41 RJ45 connector is referred as CAT 5E SECONDARY connector Signal Name CAT5E Connector Pin No 7 GAC2 IO132PDB7V1 TX1 CAT 5E PRI 1 8 IO132NDB7V1 TX1 CAT 5E PRI 2 9 IO130PDB7V1 TX2 CAT 5E PRI 5 10 IO130NDB7V1 TX2 CAT 5E PRI 4 11 IO127PDB7V1 RX1 CAT 5E PRI 3 12 IO127NDB7V1 RX1 CAT 5E PRI 6 13 IO126PDB7V0 RX2 CAT 5E PRI 7 14 IO126NDB7V0 RX...

Page 20: ...are installation instructions see the FlashPro User Guide 4 3 Testing the Starter Kit Board See Testing the Board page 19 4 4 Programming the Test File To retest the Starter Kit board at any time use the test program to reprogram the board Download the ProASIC3 E Starter Kit example design at https www microsemi com products fpga soc design resources dev kits proasic3 proasic3 starter kit document...

Page 21: ...z clock for the design The data generator Data_Block generates an eight bit up down counter and eight bit flashing signal The data generator output is displayed on the ProASIC3 E starter kit board LEDs By default an eight bit flashing signal is displayed on the LEDs The LEDs flashing direction can be changed by pressing SW4 Switch the data using the SW6 signal The counter has synchronous load and ...

Page 22: ...tches value on LEDs Press SW4 Direction control for LEDs flashing While LEDs flashing is selected with SW6 SW4 can be used to change the LEDs flashing direction Press SW5 Asynchronous clear for the whole design Press SW6 Select for DATA_BLOCK It allows switching LED output between the counter and flashing data Change Hex Switch setting U13 and U14 Changes the loaded data for the eight bit counter ...

Page 23: ... block diagram of the transmitter section of the test design programmed inside the ProASIC3 FPGA The design contains two similar channels of data Channel A is driven by a PLL to achieve high data rates and Channel B uses an external clock in the event that slow data rates are needed for test or debugging purposes Figure 5 TX Portion of Test Design Each channel uses an LFSR to generate a pseudo ran...

Page 24: ...asurement Results The following figure shows the LVDS signal across the 100 Ohm termination resistor at 300 Mbps The eye height across the termination is about 275 mV which is well within the LVDS specification Figure 6 LVDS Signal across RX Termination at 300 Mbps ...

Page 25: ...test points 7 2 Test Procedure for the A3PE STARTER KIT 2 In this section full test procedure for the boards is outlined This procedure applies to socketed boards For boards fitted with directly soldered parts the procedure is the same except for fitting of the FPGA In such cases adjust the procedure accordingly and ignore references to fitting parts to sockets 7 2 1 Initial Power On Procedure Thi...

Page 26: ...LEDs at the top of the board including the red one turn on D17 D11 D10 D9 D13 and D19 10 Validate that the 8 LEDS D8 D7 and D2 D1 all pulsate in either a counting pattern or a flashing towards left pattern 11 If no LEDs are visible stop and switch off SW11 Rotate SW8 and SW9 clockwise to the 3 3 V selection This is best described with the thicker arrow bar pointing upward Switch the board back on ...

Page 27: ... A3PE1500 part depending on the device fitted to the board has been detected then the board has passed this test Leave the silicon in place in the socket and move to the next step If a message of 11 or some other numeric indication appears then record the message in a test log and fail the board Remove the silicon from the socket and place it in the safe silicon holding area 21 This concludes the ...

Page 28: ...nd voltage referenced I O standards only w D Differential Pair or P Pair or S Single Ended D Differential Pair if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin P Pair if both members of the pair are bonded out but do not meet the adjacency requirement or S Single Ended if the I O pair is not bonded out For Differential D pairs adjacency for bal...

Page 29: ...Appendix PQ208 Package Connections UG0048 User Guide Revision 5 1 23 8 2 208 Pin PQFP The following figure shows the top view of the package Figure 7 208 Pin PQFP 208 Pin PQFP 1 208 ...

Page 30: ...PB6V0 82 IO131NDB4V2 13 IO208PDB7V2 48 GEB0 IO168NPB6V0 83 IO131PDB4V2 14 IO208NDB7V2 49 GEA0 IO167NPB6V0 84 IO129NDB4V2 15 IO204PSB7V1 50 VMV6 85 IO129PDB4V2 16 VCC 51 GNDQ 86 IO127NDB4V2 17 GND 52 GND 87 IO127PDB4V2 18 VCCIB7 53 VMV5 88 VCC 19 IO200PDB7V1 54 GNDQ 89 VCCIB4 20 IO200NDB7V1 55 IO166NDB5V3 90 IO121NDB4V1 21 IO196PSB7V0 56 GEA2 IO166PDB5V3 91 IO121PDB4V1 22 GFC1 IO192PSB7V0 57 IO165N...

Page 31: ...1 155 GNDQ 189 IO18NDB0V2 121 IO101PDB3V1 156 GND 190 IO15PDB0V1 122 GND 157 VMV1 191 IO15NDB0V1 123 VCCIB3 158 GNDQ 192 IO12PSB0V1 124 GCC2 IO90PSB3V0 159 GBA1 IO57PDB1V3 193 IO11PDB0V1 125 GCB2 IO89PSB3V0 160 GBA0 IO57NDB1V3 194 IO11NDB0V1 126 NC 161 GBB1 IO56PDB1V3 195 GND 127 IO88NDB3V0 162 GND 196 IO08PDB0V1 128 GCA2 IO88PDB3V0 163 GBB0 IO56NDB1V3 197 IO08NDB0V1 129 GCA1 IO87PPB3V0 164 GBC1 I...

Page 32: ...ides illustrations of the ProASIC3 E Starter Kit board Note The following figures are in low resolution If you would like to see the figures in high resolution refer to the ProASIC3 E Starter Kit board Schematics available at www microsemi com soc products hardware devkits_boards proasic3_starter aspx docs ...

Page 33: ...matics UG0048 User Guide Revision 5 1 27 9 1 Top Level View The following figures illustrates a top level and a bottom level view of the ProASIC3 E Starter Kit board Figure 8 Top Level View of ProASIC3 E Starter Kit Board ...

Page 34: ...Appendix Board Schematics UG0048 User Guide Revision 5 1 28 Figure 9 Bottom Level View of ProASIC3 E Starter Kit Board ...

Page 35: ...MBT2222 Q2 MMBT2222 1 2 3 U11 LM2678S 3 3 U11 LM2678S 3 3 VIN 2 ON OFF 7 GND 4 VSW 1 NC 5 CB 3 FB 6 C16 0 01UF 50V C16 0 01UF 50V 1 2 R3 200 R3 200 1 2 C2 10UF 16V C2 10UF 16V 1 2 C15 0 01UF 50V C15 0 01UF 50V 1 2 J18 CONN_KLD_SMT J18 CONN_KLD_SMT 1 2 3 D11 D11 2 1 C6 47UF 16V C6 47UF 16V 1 2 U12 TPS75218_QPWP U12 TPS75218_QPWP GND 1 NC 2 IN3 3 IN4 4 EN 5 RESET 6 SENSE 7 O P8 8 O P9 9 GND1 10 GND4...

Page 36: ...NDB3V0 120 IO58PDB3V0 121 GND_9 122 VCCIB3 123 GCC2 IO55PSB3V0 124 GCB2 IO54PSB3V0 125 NC 126 IO53NDB3V0 127 GCA2 IO53PDB3V0 128 GCA1 IO52PPB3V0 129 GND_10 130 U8F IC149 208 161 S5_21 U8F IC149 208 161 S5_21 VCCPLC 131 GCA0 IO52NPB3V0 132 VCOMPLC 133 GCB0 IO51NDB2V1 134 GCB1 IO51PDB2V1 135 GCC1 IO50PSB2V1 136 IO49NDB2V1 137 IO49PDB2V1 138 IO48PSB2V1 139 VCCIB2 140 GND_11 141 VCC_4 142 IO47NDB2V1 1...

Page 37: ...EV A U8 PIN 69 U8 PIN 70 U8 PIN 73 U8 PIN 74 U8 PIN 75 U8 PIN 76 U8 PIN 77 U8 PIN 78 U8 PIN 64 U8 PIN 66 U8 PIN 67 U8 PIN 68 DVP 100 000300 001 R27 1K R27 1K 1 2 C17 0 01UF 50V C17 0 01UF 50V 1 2 JP19 JP19 1 2 0 1 2 3 4 5 6 7 8 9 A B C D E F U13 Hex Switch 0 1 2 3 4 5 6 7 8 9 A B C D E F U13 Hex Switch 1 2 8 4 C JP17 JP17 1 2 JP23 JP23 1 2 0 1 2 3 4 5 6 7 8 9 A B C D E F U14 Hex Switch 0 1 2 3 4 5...

Page 38: ...Mgr Engr Doc Ctrl Assembly Date Title Size Document No DRAWN BY Rev Pg of BALA Microsemi Approvals Eng Mgr Engr Doc Ctrl Assembly Date Title Size Document No DRAWN BY Rev Pg of BALA SCHEMATIC DIAGRAM NOTES 1 UNLESS STATED OTHERWISE A ALL RESISTOR ARE IN OHMS 5 TOLERANCE B ALL CAPACITORS ARE IN MICROFARADS 10 TOLERANCE BOARD INFORMATION PCB FAB REV 02 PCB ASSEMBLY REV 02 FPGA Headers Expansion Bus ...

Page 39: ... 1 2 C5 0 1UF 50V C5 0 1UF 50V 1 2 R53 49 9 R53 49 9 1 2 R45 2k R45 2k 1 2 R28 1K_NL R28 1K_NL 1 2 R57 39 R57 39 R29 1K_NL R29 1K_NL 1 2 JP24 JP24 1 2 3 R37 1K_NL R37 1K_NL 1 2 JP16 JP16 1 2 R43 221K R43 221K 1 2 R58 39 R58 39 SW6 TL1105SP_F100Q SW6 TL1105SP_F100Q 1 2 3 4 U2 40MHZ OSCILLATOR NL U2 40MHZ OSCILLATOR NL EN 1 GND 2 VCC 4 OUT 3 C22 0 001UF 50V C22 0 001UF 50V 1 2 R35 332 R35 332 1 2 R3...

Page 40: ... C101 10UF 16V C101 10UF 16V 1 2 C49 0 01UF 50V C49 0 01UF 50V 1 2 TP6 TP6 C99 0 01UF 50V C99 0 01UF 50V 1 2 C37 0 01UF 50V C37 0 01UF 50V 1 2 C27 0 01UF 50V C27 0 01UF 50V 1 2 C30 0 01UF 50V C30 0 01UF 50V 1 2 C38 0 01UF 50V C38 0 01UF 50V 1 2 C47 0 01UF 50V C47 0 01UF 50V 1 2 C35 0 01UF 50V C35 0 01UF 50V 1 2 TP7 TP7 C71 10UF 16V C71 10UF 16V 1 2 C52 0 01UF 50V C52 0 01UF 50V 1 2 C72 10UF 16V C7...

Page 41: ...S SIGNAL ROUTING VIA 10 11 04 27 11 B A CAT 5E CONNECTORS 5V 500mA Max TX1 TX1 TX2 TX2 TX3 TX3 TX4 TX4 A3PE STARTER KIT BOARD REV A Impedence Control on the TX TX Traces U8 PIN 7 U8 PIN 8 U8 PIN 9 U8 PIN 10 U8 PIN 30 U8 PIN 31 U8 PIN 37 U8 PIN 38 U8 PIN 42 U8 PIN 43 U8 PIN 44 U8 PIN 45 U8 PIN 11 U8 PIN 12 U8 PIN 13 U8 PIN 14 U8 PIN 31 U8 PIN 37 U8 PIN 38 U8 PIN 8 U8 PIN 9 U8 PIN 10 U8 PIN 30 U8 PI...

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