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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

50200801 Handbook 1

6

List of Figures

Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram ......................................................................................................... 8

Figure 2 MiV_RV32IMAF_L1_AHB Block Diagram ....................................................................................................... 11

Figure 3 Example Five Stage Pipelined Architecture ................................................................................................... 12

Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View .................................................................................. 17

Figure 5 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign .................................................................................. 18

Figure 6 RTG4 Example Simulation Subsystem............................................................................................................ 18

Figure 7 MiV_RV32IMAF_L1_AHB Example System .................................................................................................... 20

Figure 8 RST Reset Synchronization ............................................................................................................................. 21

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Summary of Contents for MiV_RV32IMAF_L1_AHB

Page 1: ...HB0801 MiV_RV32IMAF_L1_AHB V2 0 Handbook 11 2017 ...

Page 2: ... anything described by such information Information provided in this document is proprietary to Microsemi and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice About Microsemi Microsemi Corporation Nasdaq MSCC offers a comprehensive portfolio of semiconductor and system solutions for aerospace defense com...

Page 3: ...he revision history describes the changes that were implemented in the document The changes are listed by revision starting with the most current publication 1 1 Release 1 0 Revision 1 0 is the first production level publication of this document Created for MiV_RV32IMAF_L1_AHB v2 0 ...

Page 4: ...stem 12 3 5 Platform Level Interrupt Controller 12 3 6 Debug support through JTAG 12 3 7 External AHB Interfaces 13 4 Interface 14 4 1 Configuration Parameters 14 4 1 1 MiV_RV32IMAF_L1_AHB Configurable Options 14 4 1 2 Signal Descriptions 14 5 Register Map and Descriptions 16 6 Tool Flow 17 6 1 License 17 6 1 1 RTL 17 6 2 SmartDesign 17 6 3 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign 17 6 4 Deb...

Page 5: ...HB0801 MiV_RV32IMAF_L1_AHB V2 0 Handbook 50200801 Handbook 1 5 8 Design Constraints 22 9 SoftConsole 24 10 Known Issues 25 10 1 Reset Power Cycle the Target Hardware before each Debug Session 25 ...

Page 6: ...V_RV32IMAF_L1_AHB Block Diagram 11 Figure 3 Example Five Stage Pipelined Architecture 12 Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View 17 Figure 5 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign 18 Figure 6 RTG4 Example Simulation Subsystem 18 Figure 7 MiV_RV32IMAF_L1_AHB Example System 20 Figure 8 RST Reset Synchronization 21 ...

Page 7: ...es Table 1 Device Utilization and Performance 9 Table 2 MiV_RV32IMAF_L1_AHB Architecture 10 Table 3 Example Pipeline Timing 12 Table 4 MiV_RV32IMAF_L1_AHB Configuration Options 14 Table 5 MiV_RV32IMAF_L1_AHB I O Signals 14 Table 6 Physical Memory Map from E3 Coreplex Series 16 ...

Page 8: ...32 bit RISC V core The core includes an industry standard JTAG interface to facilitate debug access along with separate AHB bus interfaces for memory access and support for 31 dedicated interrupt ports Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram MiV_RV32IMAF_L1_AHB JTAG I F External Interrupts AHB Memory I F AHB MMIO I F Debug Transport Module Debug Module E31 Core Uncached TileLink Interconnect Ti...

Page 9: ...ual Volume 1 User Level ISA Version 2 1 The RISC V Instruction Set Manual Volume 2 Privileged Architecture Version 1 10 2 4 Supported Families PolarFire RTG4 IGLOO 2 SmartFusion 2 2 5 Device Utilization and Performance Utilization and performance data is listed in Table 1 for the supported device families The data listed in this table is indicative only The overall device utilization and performan...

Page 10: ...e Static Not Taken Multiplier occupancy 16 cycles 2 bit cycles iterative multiply I cache size 8 KiB I cache associativity 1 way direct mapped I cache line size 64 bytes D cache size 8 KiB D cache associativity 1 way direct mapped D cache line size 64 bytes Reset Vector configurable External interrupts 31 PLIC Interrupt priorities 1 Fixed priorities External memory bus AHB External I O bus AHB JTA...

Page 11: ...essor Core MiV_RV32IMAF_L1_AHB is based on the E31 Coreplex Core by SiFive The core provides a single hardware thread or hart supporting the RISC V standard RV32IMAF ISA and machine mode privileged architecture 3 3 Pipelined Architecture MiV_RV32IMAF_L1_AHB provides a high performance single issue in order 32 bit execution pipeline with a peak sustainable execution rate of one instruction per cloc...

Page 12: ...rdware cache flushing as well as uncached memory accesses External connections are provided for both cached and uncached TileLink fabrics 3 5 Platform Level Interrupt Controller MiV_RV32IMAF_L1_AHB includes a RISC V standard platform level interrupt controller PLIC configured to support up 31 inputs with a single priority level 3 6 Debug support through JTAG MiV_RV32IMAF_L1_AHB includes full exter...

Page 13: ...Interfaces MiV_RV32IMAF_L1_AHB includes two external AHB interfaces bridged from the internal TileLink interfaces The AHB memory interface is used by the cache controller to refill the instruction and data caches The AHB I O interface is used for uncached accesses to I O peripherals ...

Page 14: ...le 5 Table 5 MiV_RV32IMAF_L1_AHB I O Signals Port Name Width Direction Description Global Signals CLK 1 In System clock All other I Os are synchronous to this clock RESETN 1 In Synchronous reset signal Active Low JTAG Interface Signals TDI 1 In Test Data In TDI This signal is used by the JTAG device for downloading and debugging programs Sampled on the rising edge of TCK TCK 1 In Test Clock TCK Th...

Page 15: ...Out AHB_MST_MEM_HWRITE 1 Out AHB_MST_MEM_HADDR 32 Out AHB_MST_MEM_HSIZE 3 Out AHB_MST_MEM_HBURST 3 Out AHB_MST_MEM_HPROT 4 Out AHB_MST_MEM_HWDATA 32 Out AHB_MST_MEM_HREADY 1 In AHB_MST_MEM_HRESP 1 In AHB_MST_MEM_HRDATA 32 In AHB Non cached Memory Bus Interface AHB_MST_MMIO_HLOCK 1 Out AHB Master Interface for non cached memory accesses AHB_MST_MMIO_HTRANS 2 Out AHB_MST_MMIO_HWRITE 1 Out AHB_MST_MM...

Page 16: ...set 0x0000_1004 NMI 0x0000_1008 Reserved 0x0000_100C Configuration string address 0x0000_1010 0x0000_XXXX Trap vector table start Small ROM Area 60 KiB 0x0000_XXXX Reset code Interrupt handlers Emulation routines Register save restore routines 0x0000_FFFF User ROM 0x0001_0000 0x3FFF_FFFF Reserved ROM Misc Reserved 1GiB 0x4000_0000 0x43FF_FFFF Platform Level Interrupt Control PLIC 0x4400_0000 0x47F...

Page 17: ...ign Simulation Synthesis and Layout can be performed within Libero SoC 6 2 SmartDesign MiV_RV32IMAF_L1_AHB is preinstalled in SmartDesign IP Deployment design environment For more information on using SmartDesign to instantiate and generate cores refer to the Using DirectCore in Libero SoC User Guide Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View 6 3 Configuring MiV_RV32IMAF_L1_AHB in Smar...

Page 18: ...ng of MiV_RV32IMAF_L1_AHB This is available in the Libero Catalog 6 5 Simulation Flows The user testbench for MiV_RV32IMAF_L1_AHB is not included in this release The MiV_RV32IMAF_L1_AHB RTL can be used to simulate the processor executing a program using a standard Libero generated HDL testbench An example subsystem for RTG4 is as shown in Figure 6 Figure 6 RTG4 Example Simulation Subsystem ...

Page 19: ...set the SmartDesign sheet as the design root and click Synthesis in Libero SoC 6 7 Place and Route in Libero After the design is synthesized run the compilation and the place and route tools Click Layout in the Libero SoC to invoke Designer MiV_RV32IMAF_L1_AHB requires the place and route multi seed settings set to 5 ...

Page 20: ...ronization 7 2 1 RST All sequential elements clocked by CLK within MiV_RV32IMAF_L1_AHB which require a reset employ a synchronous reset topology Since most designs source CLK from a CCC PLL it is common practice to AND the LOCK output of the CCC with the push button reset to generate the RST input for MiV_RV32IMAF_L1_AHB However this results in the reset being deasserted when the CLK comes up henc...

Page 21: ...lock or negedge reset begin if reset begin sync_deasert_reg 1 0 2 b00 end else begin sync_deasert_reg 1 0 sync_deasert_reg 0 1 b1 end end always posedge clock begin sync_asert_reg 1 0 sync_asert_reg 0 sync_deasert_reg 1 end assign reset_sync sync_asert_reg 1 endmodule To include this synchronizer in your Libero design select Create HDL from the Design Flow tab in your Libero project In the popup w...

Page 22: ...e and name it Design constraints other than the system clock source derived constraints can be entered in this blank SDC file Keeping derived and manually added constraints in separate SDC files allows the Derive stage to be reperformed if changes are made to the PLL configuration without deleting all manually added constraints in the process 3 Calculate the TCK period and half period TCK is typic...

Page 23: ...T_28_data ii MIV_RV32IMAF_L1_AHB_0 ChiselTop0 tile rocket fpuOpt sfma _T_28_exc For example set_multicycle_path setup_only 2 through MIV_RV32IMAF_L1_AHB_0 ChiselTop0 tile rocket fpuOpt sfma _T_28_data set_multicycle_path setup_only 2 through MIV_RV32IMAF_L1_AHB_0 ChiselTop0 tile rocket fpuOpt sfma _T_28_exc 6 Associate all constraints files with the Synthesis Place and Route and Timing Verificatio...

Page 24: ... 9 SoftConsole SoftConsole Version 5 2 is required to use MiV_RV32IMAF_L1_AHB Each SoftConsole project requires the Hardware Abstraction Layer HAL version 2 1 or greater The SoftConsole Release Notes details how to set up a project for the MiV_RV32IMAF_L1_AHB core ...

Page 25: ...able Mi V RISC V CPU SoC reset at the start of each debug session so one debug session may be impacted by what went before for example a previous debug session leaves the CPU in an ISR and a subsequent debug session does not behave as expected because of this To mitigate this problem it is recommended that the target hardware board is power cycled or otherwise reset before each new debug session ...

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