HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook
50200801 Handbook 1
8
2
Introduction
2.1
Overview
The MiV_RV32IMAF_L1_AHB is a softcore processor designed to implement the RISC-V instruction
set for use in Microsemi FPGAs. The processor is based on the Coreplex E31 designed by SiFive,
containing a high-performance single-issue, in-order execution pipeline E31 32-bit RISC-V core. The
core includes an industry-standard JTAG interface to facilitate debug access, along with separate
AHB bus interfaces for memory access and support for 31 dedicated interrupt ports.
Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram
MiV_RV32IMAF_L1_AHB
JTAG I/F
External
Interrupts
AHB Memory I/F
AHB MMIO I/F
Debug
Transport
Module
Debug Module
E31 Core
Uncached TileLink Interconnect
TileLink to
AHB Bridge
TileLink to
AHB Bridge
Platform-Level Interrupt
Controller
8 KB Instruction Cache
RV32IMAF
Integer Multiplier/Divider
8 KB Data Cache
