HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook
50200801 Handbook 1
17
6
Tool Flow
6.1
License
This core is being released under a modified Apache 2.0 license and is freely available through
Libero. Technical support is only provided for Microsemi Products.
6.1.1
RTL
Complete Verilog source code is provided for the core. A VHDL wrapper is provided for use in VHDL
projects. Allowing the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout
can be performed within Libero SoC.
6.2
SmartDesign
MiV_RV32IMAF_L1_AHB is preinstalled in SmartDesign IP Deployment design environment.
For more information on using SmartDesign to instantiate and generate cores, refer to the
Using
DirectCore in Libero® SoC User Guide
.
Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View
6.3
Configuring MiV_RV32IMAF_L1_AHB in SmartDesign
The core is configured using the configuration GUI within SmartDesign, as shown in
Figure 5
.
Note
: Leading zeros are suppressed, for example, 0x6000 0000 is displayed as 0x6000 0x0. The reset
vector is byte aligned.