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Figure 5-5. DDR2-SDRAM
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Keep nets as short as possible, therefore, DDR devices have to be placed close as possible of SAMA5D27
The layout DDR should use controlled impedance traces of ZO= 50ohm characteristic impedance.
Address, control and data traces may not exceed 1.3 inches (33.0 mm).
Address, control and data traces must be length-matched to within 0.1 inch (2.54mm).
Address, control and data traces must match the data group trace lengths to within 0.25 inches (6.35mm).
2 x W972GG6KB-25, DDR2-800, 16 Meg x 16 x 8
RevB
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
D
DDR_DQS0-
D
DDR_DQS1-
D
DDR_DQS2-
D
DDR_DQS3-
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_RAS
DDR_CAS
DDR_BA2
DDR_CS
DDR_WE
DDR_CLK-
DDR_VREF
DDR_RESETN
DDR_CLK-
DDR_CKE
DDR_VREF
DDR_VREF
DDR_VREF
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0-
D
D
DDR_DQS1-
D
DDR_DQS2-
D
DDR_DQS3-
DDR_BA1
DDR_BA0
DDR_BA1
DDR_BA0
DDR_WE
DDR_WE
DDR_CS
DDR_CS
DDR_CLK-
DDR_CLK-
DDR_CKE
DDR_CKE
DDR_CAS
DDR_RAS
DDR_CAS
DDR_RAS
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_BA2
DDR_BA2
DDR_A13
DDR_A13
GND_POWER
GND_POWER
GND_POWER
VDD_1V8
GND_POWER
VDD_1V8
GND_POWER
GND_POWER
GND_POWER
VDDIODDR
GND_POWER
VDD_1V8
GND_POWER
VDD_1V8
GND_POWER
GND_POWER
VDD_1V8
GND_POWER
VDD_1V8
GND_POWER
VDDIODDR
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
5
13
B
XX-XXX-XX
ZhouB
XXX
05) DDR2-SDRAM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
5
13
B
XX-XXX-XX
ZhouB
XXX
05) DDR2-SDRAM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
5
13
B
XX-XXX-XX
ZhouB
XXX
05) DDR2-SDRAM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
C86
100nF
C0402
R23
100K
R0402
C65
4.7uF
C0805
C68
10uF
C0603
R24
21K-1%
R0402
C87
100nF
C0402
C69
10uF
C0603
C94
100nF
C0402
C73
1uF
C0603
C90
1nF
C0402
R29
DNP
R0402
R25
100K
R0402
C64
22pF
C0402
C66
100nF
C0402
C74
1uF
C0603
C91
1nF
C0402
C76
100nF
C0402
C92
1nF
C0402
C95
1nF
C0402
C77
100nF
C0402
C93
1nF
C0402
C78
100nF
C0402
C88
1nF
C0402
ATSAMA5D27C-CN
U6E
bga289p8
DDR_A0
F12
DDR_A1
C17
DDR_A10
C15
DDR_A11
A16
DDR_A12
A17
DDR_A13
G11
DDR_A2
B17
DDR_A3
B16
DDR_A4
C16
DDR_A5
G14
DDR_A6
F14
DDR_A7
F11
DDR_A8
C14
DDR_A9
D13
DDR_BA0
H12
DDR_BA1
H13
DDR_BA2
F17
DDR_CAL
E13
DDR_CAS
G12
DDR_CKE
F16
DDR_CLK
E17
DDR_CLKN
D17
DDR_CS
G13
DDR_D0
B12
DDR_D1
A12
DDR_D10
H17
DDR_D11
K17
DDR_D12
K16
DDR_D13
J13
DDR_D14
K14
DDR_D15
K15
DDR_D16
B8
DDR_D17
B9
DDR_D18
C9
DDR_D19
A9
DDR_D2
C12
DDR_D20
A10
DDR_D21
D10
DDR_D22
B11
DDR_D23
A11
DDR_D24
J12
DDR_D25
H10
DDR_D26
J11
DDR_D27
K11
DDR_D28
L13
DDR_D29
L11
DDR_D3
A13
DDR_D30
L12
DDR_D31
M17
DDR_D4
A14
DDR_D5
C13
DDR_D6
A15
DDR_D7
B15
DDR_D8
G17
DDR_D9
G16
DDR_DQM0
C11
DDR_DQM1
G15
DDR_DQM2
C8
DDR_DQM3
H11
DDR_DQS0
B13
DDR_DQS1
J17
DDR_DQS2
C10
DDR_DQS3
L17
DDR_DQSN0
B14
DDR_DQSN1
J16
DDR_DQSN2
B10
DDR_DQSN3
L16
DDR_RAS
F13
DDR_RESETN
E16
DDR_VREFCM
D16
DDR_VREFB0
H16
DDR_WE
F15
R28
DNP
C79
100nF
C0402
C89
1nF
C0402
U8
W972GG6KB-25
bga84-32-1509e
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
A13
R8
BA0
L2
BA1
L3
BA2
L1
CKE
K2
CK_P
J8
CK_N
K8
RAS
K7
CAS
L7
WE
K3
CS
L8
DQ0
G8
DQ1
G2
DQ2
H7
DQ3
H3
DQ4
H1
DQ5
H9
DQ6
F1
DQ7
F9
DQ8
C8
DQ9
C2
DQ10
D7
DQ11
D3
DQ12
D1
DQ13
D9
DQ14
B1
DQ15
B9
LDQS_P
F7
NU/LDQS_N
E8
UDQS_P
B7
NU/UDQS_N
A8
LDM
F3
UDM
B3
ODT
K9
NC1
A2
NC2
E2
NC3
R3
NC4
R7
VDD1
A1
VDD2
E1
VDD3
J9
VDD4
M9
VDD5
R1
VDDQ1
A9
VDDQ2
C1
VDDQ3
C3
VDDQ4
C7
VDDQ5
C9
VDDQ6
E9
VDDQ7
G1
VDDQ8
G3
VDDQ9
G7
VDDQ10
G9
VDDL
J1
VREF
J2
VSS1
A3
VSS2
E3
VSS3
J3
VSS4
N1
VSS5
P9
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VSSDL
J7
R27
2.2K-1%
R0402
C80
100nF
C0402
C81
100nF
C0402
U7
W972GG6KB-25
bga84-32-1509e
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
A13
R8
BA0
L2
BA1
L3
BA2
L1
CKE
K2
CK_P
J8
CK_N
K8
RAS
K7
CAS
L7
WE
K3
CS
L8
DQ0
G8
DQ1
G2
DQ2
H7
DQ3
H3
DQ4
H1
DQ5
H9
DQ6
F1
DQ7
F9
DQ8
C8
DQ9
C2
DQ10
D7
DQ11
D3
DQ12
D1
DQ13
D9
DQ14
B1
DQ15
B9
LDQS_P
F7
NU/LDQS_N
E8
UDQS_P
B7
NU/UDQS_N
A8
LDM
F3
UDM
B3
ODT
K9
NC1
A2
NC2
E2
NC3
R3
NC4
R7
VDD1
A1
VDD2
E1
VDD3
J9
VDD4
M9
VDD5
R1
VDDQ1
A9
VDDQ2
C1
VDDQ3
C3
VDDQ4
C7
VDDQ5
C9
VDDQ6
E9
VDDQ7
G1
VDDQ8
G3
VDDQ9
G7
VDDQ10
G9
VDDL
J1
VREF
J2
VSS1
A3
VSS2
E3
VSS3
J3
VSS4
N1
VSS5
P9
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VSSDL
J7
C82
100nF
C0402
C67
100nF
C0402
C72
100nF
C0402
R32
0R
R0402
C83
100nF
C0402
C75
1nF
C0402
R26
2.2K-1%
R0402
C84
100nF
C0402
C62
100nF
C0402
C85
100nF
C0402
C63
100nF
C0402
R31
DNP
R0402
C70
1uF
C0603
C71
1uF
C0603
R30
0R
R0402
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
©
2017 Microchip Technology Inc.
DS50002709A-page 53