ZLR964222L
Line Module User Guide
19
Microsemi Corporation Confidential and Proprietary
5.0 Module Configuration
5.1 Introduction
The
ZLR964222L Line Module
is programmed through the
VoicePath Application Program Interface (VP-API-II)
.
This API hides the complexity of the device and its internal registers and provides a much simpler interface to the
software engineer. The
VP-API-II
software requires
Profiles
to initialize the AC, DC, signaling, supervision, host
interface, and switcher settings. Default
Profile
values are stored on Module ID ROM (MID) memory devices on the
line modules to enable "out-of-the-box" operation. Most profiles can be easily modified using the
Profile Wizard
software tool.
5.2 Module ID ROM (MID) Default Profiles
The MID
ZLR964222L
include
AC, Tone, Cadence
, and
Caller ID Profiles
. They have different
Device
,
DC
, and
Ringing Profiles
, since the switcher output voltage, low-power idle mode, and ringing amplitude and characteristics
are not the same.
5.2.1 Device Profile
The
Device Profile
sets the PCM clock (PCLK or ZCLK) frequency, PCM transmit edge, transmit and receive clock
slots. The VBAT power supply parameters are also configured from the device profile.
5.2.2 AC Profile
Used for programming the transmission characteristics of the system, the AC Profile holds the programmable gain
and filter coefficient data.
The default
AC Profile
provides a 600
input and balance impedance with -6 dBr receive level and 0 dBr transmit.
It also takes into account the nominal 5
PTC series resistance per leg.
5.2.3 DC Profile
The
DC Profile
contains the parameters for the
ZLR964222L Line Module
to control supervision thresholds, DC
feed, and other switcher settings. It is not compatible with the
DC Profiles
that were used for the
VE880 and VE890
due to new features in the
miSLIC
devices. miSLIC devices are compatible with ZL880 device DC profiles.
The MID settings for the
DC Profile
include an Open Circuit Voltage (VOC) of 48 V, and an Active Mode Current
Limit (I
LA
) of 23 mA. The loop hook detection thresholds are 11 mA for the
Active
state and 22 V for the
Low Power
Idle Mode
state. The hook debounce time is 12 ms. The Ground Key detection threshold is 18 mA with 16 ms
debounce.
5.2.4 Ringing Profile
The
Ringing Profile
is set in the
ZLR964222L
MID to generate a 70 V
PK
(50 V
RMS
) with no DC offset at 25 Hz. Ring
trip is set to integrate over half-wave (AC only) with a ring trip threshold (R
TTH
) of 62.5 mA. The ringing current limit
(I
LR
) set to 45 mA. The ringing profile is optimized for 5REN maximum loads at 50Vrms.
5.2.4.1 Ringing Power Management (RPM)
The ZLR964222L module supports Ringing Power Management
.
This feature allows for limting input current during
ringing. When enabled, ring voltage can be reduced when heavy REN loads are encountered. Refer to section 6.7
for more detatils on RPM.
