ZLR964222L
Line Module User Guide
38
Microsemi Corporation Confidential and Proprietary
1ohm resistor is placed between DVDD and AVDD and a 4.7uF ceramic cap is connected from AVDD to ground.
The value of the resistor should not be increased or AVDD voltage may become degraded and out of spec.
One common source of EMI is exceedingly fast edge rates on digital signals. Modern CMOS processes result in
digital edge rates that have no problem achieving 1 ns rise/fall times. This results in spectral components that are
well into the GHz range. This is completely unnecessary for proper device operation. Even with careful design and
layout, significant overshoots on clock edges are present that can result in noise in the device and even EMI failure
due to this noise creeping out the tip and ring pair. In many cases, placing a 100
series termination resistor at the
source will slow the edges down to 5 ns, which is still well within the rise time requirements of miSLIC
devices.
What this achieves is that the rise/fall time is slow enough that transmission line effects are no longer a factor in
many cases. This has been shown to result in very nice square clocks with little or no overshoot.
For best thermal performance of the QFN-48 package, the
Le9642
, thermal pad must be soldered to a thermal pad
under the device. If the board is a two-layer design, the thermal pad should also be on the back side of the PCB
with an array of vias connecting both sides. To maintain consistent ground coverage on the back side of the PCB,
all components are placed on the top side. Traces should also routed on the top side as much as possible around
the device. Routes on the bottom side will limit the flow of heat away from the device. The more copper the better. If
the design incorporates a ground plane, the thermal pad should tie into the ground plane with a 7x7 array of 13 mil/
0.33 mm vias on a 5.4x5.4 mm area. The vias should be hard tied into the bottom side ground plane. Thermal
(wagon wheel) vias should not be used. Note that ALL ground connections for this device are through the ePAD,
therefore the ePAD MUST be grounded for both electrical and thermal reasons.
Use of the ZSI interface is encouraged for 2 layer designs, as this reduces the number of signals that need to be
routed. When using the ZSI interface, it is not necessary to place pull up or pull down resistors on the unused MPI
interface pins. If resistors are used, they should be placed away from the device to prevent crowding around the
device. If the resistors are placed next to the pins, this forces the ground layer on the bottom side to be significantly
cut up
Under some operating conditions the thermal stress on the PNP power transistor (Q1) can be quite high. The
collector tab of the PNP transistor should have a minimum PCB pad of 1cm x 1cm. More copper is better, but noise
influence must also be considered. The collector node should never be placed close to the SWIS current sense net.
Noise from the PNP collector can couple into the SWIS net and disrupt the stability of the power supply.
Although this design is shown as a two-layer design, best performance can be achieved with a multilayer design
that incorporates ground planes.
7.3 ZLR964222L Line Module Schematics
The schematics of the Le9642-based
ZLR964222L Line Module
are provided below . Please refer Bill of Material in
Section 7.4 for details about component selections.
The module schematic is available in
Cadence OrCAD V16.5 (Allegro Design Entry CIS)
format upon request
