dsPIC30F Demonstration Program Operation
©
2006 Microchip Technology Inc.
DS70099D-page 39
3.4.3.6
TIMER1
Timer1 is a 16-bit timer that uses the instruction cycle as its time base. It is configured
to time out and generate an interrupt every 125 microseconds. The Timer1 Interrupt
Service Routine (ISR) loads the SPI 2 buffer with a value from a sine table. The SPI 2
module is then used to transmit the sine sample to digital potentiometer MCP41010.
The MCP41010 output is connected to pin AN3/RB3 of the dsPIC30F device.
3.4.3.7
TIMER2
LEDs 1-4 count upward in binary form from 0 through 15. The count rate is controlled
by the 16-bit Timer2 module, which expires every second as it is operated in a 256:1
prescale mode, with the instruction cycle being the count interval.
3.4.3.8
TIMER3
The Timer3 count is configured to expire every 1.14 seconds. In the Timer3 ISR, a
software flag is used to determine whether data needs to be updated to the PC via the
UART2 module. Thus data is not transmitted to the PC all the time so that the data on
the HyperTerminal window is legible. Data sent to the LCD, however, is refreshed
continuously since it does not have a “scrolling” effect.
3.5
dsPIC30F DEMONSTRATION PERFORMANCE METRICS
The dsPIC30F performance metrics are primarily based upon acquisition and
processing of the 256 discrete samples. The discrete samples are acquired by the ADC
sampling of a sine-wave signal applied to analog channel input AN3.
The sine-wave signal is generated as a result of stepping the MCP41010 digital
potentiometer at an 8 kHz rate with its output applied to a low-pass filter with a cutoff
frequency of approximately 4 kHz.
This acquisition and processing sequence repeats in a continuous loop.
Upon user command via the LCD menu system (or optionally from PC keys <0>-<9>),
DTMF tones are generated. During this time additional CPU MIPS are required.
This demonstration was developed for the development board that is supplied with a
7.3728 MHz crystal. The dsPIC30F is programmed for the XTx4PLL mode of
operation, effectively yielding 7.3728 MIPS. Additional MIPS are not required for this
demo but could have been obtained by using the XTx8PLL and XTx16PLL modes of
operation yielding 14.7456 and 29.4912 MIPS.
Note:
The demo code as supplied has specific timing parameters derived from
the 7.3728 MHz crystal with the XTx4PLL mode. Changing the device time
base will require modification of several time-specific parameters.
