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Register Description
IF2008/PCIe / IF2008E
Counting direction
Bit 4 Counting direction
Fig. 26: Encoder interpolation
0
normal
1
inversed
Counter mode:
Bit 7 Bit 6 Bit 5 Counter mode
0
0
0
No counter load / delete function by encoder reference marker
0
0
1
Counter is loaded with the next encoder reference marker provi-
ded that the state bit 0 or state bit 2 “0” is settled.
0
1
0
Counter is loaded including all encoder reference markers and
load register content. State bit 0 to 3 have no effect.
0
1
1
Counter is deleted including all encoder reference markers and
additionally loaded with the content of the load register if the
counter has reached -1. This function offers the possibility to
limit the counter. During this process the counter load register
has to be preallocated with the number of increments limited -1.
1
0
0
Counter without phase discriminator (event counter)
Bit 4
Function
0
Track A = counter direction signal
Track B = counter clock signal
1
Track A = counter clock signal
Track B = counter direction signal
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Fig. 27: Counter mode
Interpolation
Bit 3 Bit 2 Bit 1 Bit 0 Interpolation
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
8
0
1
1
1
10
1
0
0
0
12
1
0
0
1
16
1
0
1
0
20
Bit 3 Bit 2 Bit 1 Bit 0 Interpolation
1
0
1
1
24
1
1
0
0
32
1
1
0
1
40
1
1
1
0
48
1
1
1
1
64
Fig. 25: Encoder interpolation
i
For encoders with 1-Vss signals all
interpolations are suitable.
For encoders with TTL-signals the
following interpolations are suitable:
1, 2 or 4 times.
