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Register Description
IF2008/PCIe / IF2008E
10.7
Interrupt-Status-Register
Base addr. + 06h (read access)
Bit Function
0
1 = Interrupt requirement if FIFO level exceeds 50 %
1
1 = Interrupt requirement if FIFO level exceeds 75 %
2
1 = Interrupt requirement on overflow Timer 1
3
1 = Interrupt requirement on overflow Timer 2
4
1 = Interrupt requirement on overflow Timer 3
5
1 = Interrupt requirement if external input IN 1 is acti-
vated
6
1 = Interrupt requirement if external input IN 2 is acti-
vated
7
1 = Interrupt requirement if external input IN 3 is acti-
vated
8
1 = Interrupt requirement if external input IN 4 is acti-
vated
9 - 15 Reserved
Fig. 21: Interrupt status register
i
The interrupt state register informs by which source(s)
the interrupt requirements have been generated. One
interrupt requirement can be effected by using more than
one source at the same time. In case that no state bit is
set, the interrupt requirement was not generated by the
IF2008A but by another hardware.
10.6
Interrupt Enable Register
Base addr. + 06h (write access)
Bit Function
0
1 = Enable interrupt requirements if FIFO is filled with
more than 50 %
1
1 = Enable interrupt requirements if FIFO is filled with
more than 75 %
2
1 = Enable interrupt requirements on overflow Timer 1
3
1 = Enable interrupt requirements on overflow Timer 2
4
1 = Enable interrupt requirements on overflow Timer 3
5
1 = Enable interrupt requirements if external input IN 1
is activated
6
1 = Enable interrupt requirements if external input IN 2
is activated
7
1 = Enable interrupt requirements if external input IN 3
is activated
8
1 = Enable interrupt requirements if external input IN 4
is activated
9 - 15 Reserved
Fig. 20: Interrupt enable register
i
The interrupt generation is controlled by a trigger flan-
ge, i.e., an interrupt requirement is only effected if the
corresponding bit is set in the interrupt enable register.
Furthermore, the appropriate source has to change from
the inactive into the active state. Several bits can be set at
the same time.
