KSZ8851SNL-Eval Evaluation Board User’s Guide
Rev. 1.1
Micrel, Inc.
April 21, 2010
7/11
4.1 Host SPI Interface
The KSZ8851SNL supports a SPI interface in slave mode. In this mode, a external SPI master
device (micro-controller or CPU) supplies the operating serial clock (SCLK), chip select (CSN)
and serial input data (SI) which is clocked in on the rising edge of SCLK to KSZ8851SNL device.
Serial output data (SO) is driven out by the KSZ8851SNL on the rising edge of SCLK to external
SPI master device. The falling edge of CSN is starting the SPI operation and the rising edge of
CSN is ending the SPI operation. The SCLK stays low state when SPI operation is idle. Figure 6
shows the SPI interface connection for KSZ8851SNL.
Figure 2. SPI Interface to KSZ8851SNL
The KSZ8851SNL-Eval board re5V power from the header JP1 (pin 1). Figure 3 shows
the Host SPI interface connection with Spirent SmartBits for system set-up and performance test.
Any Microcontroller
Hardware Platform with
SPI Interface
SmartBits
SX-7410
Module
Spirent
SmartBits
2000
Chassis
KSZ88851SNL
-EVAL
RJ-45
SPI I/F
JP
1
J1
Figure 3. KSZ8851SNL-Eval Host SPI Interface Connection with Spirent SmartBits
The KSZ8851SNL-Eval has a 10-pin header (JP1) for Host SPI interface to any external
Microcontroller hardware platform. Table 1 lists 4-wire SPI pin outs for the Host interface on
header JP1. Table 2 lists the rest of control signals and power/ground pin outs for the Host
interface on header JP1.
