5I25 15
OPERATION
LEDS
The 5I25 has 2 FPGA driven user LEDs (User 0 and User 1 = Green), and 2 status
LEDs (red). The user LEDs can be used for any purpose, and can be helpful as a simple
debugging feature. A low output signal from the FPGA lights the LED. See the 5I25IO.PIN
file for FPGA pin locations of the LED signals. The status LEDs reflect the state of the
FPGA’s DONE, and /INIT pins. The /DONE LED lights until the FPGA is configured at
power-up. The /INIT LED lights when the power on reset is asserted, when there has been
a CRC error during configuration. When using Mesas configurations, the /INIT LED blinks
when the fallback configuration has been loaded.
PULLUP RESISTORS
All I/O pins are provided with pull-up resistors to allow connection to open drain,
open collector, or OPTO devices. These resistors have a value of 3.3K so have a
maximum pull-up current of 1.5 mA (5V pull-up) or 1 mA (3.3V pull-up).
IO LEVELS
The Xilinx FPGAs used on the 5I25 have programmable I/O levels for interfacing
with different logic families. The 5I25 does not support use of the I/O standards that require
input reference voltages. All standard Mesa configurations use LVTTL levels.
Note that even though the 5I25 can tolerate 5V signal inputs, its outputs will not
swing to 5V. The outputs are push pull CMOS that will drive to the output supply rail of
3.3V. This is sufficient for TTL compatibility but may cause problems with some types of
loads. For example when driving an LED that has its anode connected to 5V, in such
devices as OPTO isolators and I/O module rack SSRs, the 3.3V high level may not
completely turn the LED off. To avoid this problem, either drive loads that are ground
referred, Use 3.3V as the VCC for VCC referred loads, or use open drain mode.
STARTUP I/O VOLTAGE
After power-up or system reset and before the the FPGA is configured, the pull-up
resistors will pull all I/O signals to a high level. If the FPGA is used for motion control or
controlling devices that could present a hazard when enabled, external circuitry should be
designed so that this initial state results in a safe condition.
