5I25 13
OPERATION
SPI INTERFACE DESCRIPTION
This is the register level description of the simple SPI interface to the 5I25's
configuration EEPROM. This hardware is built into all Mesa 5I25 configurations. This
information is only needed if you are writing your own programming utility.
DATA REGISTER at offset 0x74 from 5I25 base address
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CONTROL REGISTER at offset 0x70 from 5I25 base address
X
X
X
X
X
DAV
BUSY
CS
X
X
X
X
X
R/O
R/O
R/W
