MT3620
Hardware User Guide
MediaTek Confidential
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2020 MediaTek Inc.
Page 22 of 40
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8.2
MT3620 Power Plan
Internally to the MT3620, the 3.3V power source is directly supplied to the switching regulator, digital
I/Os and RF related circuitry. It’s converted to 2.5V by the LDO for e-fuse and ADC analog circuitry,
and it’s converted to 1.6V by the switching regulator for low voltage circuits. The built-in digital LDOs
and RF LDOs convert 1.6V to 1.15V for digital, RF, and BBPLL core circuits.
The following figure describes the MT3620 power tree.
Table 8-1 MT3620 Power Rail Table
Voltage
Source
Default State
Usage
Comment
3.3V
external power supply
--
PMU, IO , RTC and RF
*3 (both RTC 3.3v and
the common 3.3v
supply)
2.5V
ALDO
off
ADC analog macro
*3
2.5V
ELDO
off
e-fuse macro
*3
1.6V
Buck (normal mode/low power
mode)
BUCK on
RF and XTAL
*3
1.15V
CLDO (normal mode/low power
mode)
CLDO on
Digital core logic
*3
We strongly recommend using decoupling capacitors on each power rail.
8.2.1
PMU Buck 3.3V Supply Input
Several items are noticed here,
For 3.3V source recommend specifications
1. AC+DC 3.3V ±10% (2.97V~3.63V )
2. PWM Ripple < 10 mVpk-pk @ 1.1A
3. Load Transient Drop and overshoot ±100mV @3.3V Iout=0 to 1.1A
4. Imax >= 1.1A (For Buck and LDO Inrush current)
0.1uF capacitor
(C52) should be close to Pin AVDD_3V3_BUCK(88,89) and PMU_CAP(87). 10uF
capacitors (C49,C50) are behind 1uF (C90) and close to AVDD_3V3_BUCK (88,89) as following
Figure 8-2. The trace width from 3.3V power source to chipset (AVDD_3V3_BUCK pins) should
be ≥ 0.64mm. AVSS_3V3_BUCK (92,93) should wire 0.64mm least trace to C49 and C50 GND
pin first, then vias to ground plane.
PCB constrain”C90 to pin 88/89 PCB parasitic L + C90 to pin 92/93 PCB parasitic L” < 1.5 nH
This is for reliability to protect large bonding inductance in package.
