MT3620
Hardware User Guide
MediaTek Confidential
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2020 MediaTek Inc.
Page 30 of 40
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The 4.7uF cap provides additional smoothing when switching between battery and main 3V3
(there is also a 100nF capacitor on the 3V3_RCT line (not shown above), located close to the
MT3620)
8.4
Power/GND Checklist
Table 8-3 specifies the checklist and guidelines for power and GND routing.
Table 8-3. Checklist for Power and GND Routing
Item
Type
Description
Ref
section
[1] Power Capacitor Design guideline
1-1 Suggestion A decoupling capacitor (0.1uF) is suggested for each power pin.
N/A
1-2 Mandatory Decoupling capacitors (0.1uF) must be placed as close as possible to power pins.
N/A
1-3 Mandatory Decoupling capacitors (0.1uF) must have a low loop inductance.
N/A
1-4 Mandatory
Larger decoupling capacitors (10uF, 2.2uF, 1uF) must be placed as close as
possible beside the relevant power pins.
N/A
1-5 Mandatory Larger decoupling capacitors (10uF, 2.2uF, 1uF) is required power shape with
multi-vias or high current Via for power\GND.
N/A
1-6 Mandatory
Buck 3.3V input parasitic from pin to capacitor need to meet 1.5nH spec.
“The inductance of C90 to AVDD_3V3_BUCK + The inductance of C90 to
AVSS_3V3_BUCK”<1.5nH
Buck input capacitor should be close to the IC to reduce parasitic inductance.
4.2.1
