MEDIATEK MT3620 Hardware User'S Manual Download Page 23 | Manualshive

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MT3620

Hardware User Guide

MediaTek Confidential

©

2020 MediaTek Inc.

Page 23 of 40

This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure

of this information in whole or in part is strictly prohibited.

Figure 8-2 PMU Buck Circuit and Layout Placement

VOUT_1V6

Inductor

AVDD_3V3_Buck

AVSS_3V3_Buck

Cin Cap

Ground

Plane

VIA

VIA

VIA

VIA

Ground

Plane

Cout Cap

Layer 1

Layer 1

Layer 1

GND & EPAD

Ground

Plane

Before connect to Cin Cap,
Buck_GND can not connect
to ground plane and GND
PAD directly

Figure 8-3 PMU Buck Ground Layout

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Summary of Contents for MT3620

Page 1: ...MediaTek Inc Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited Specifications are subject to change without notice Version v2 0 Release Date 2019...

Page 2: ...2 of 40 This document contains information that is proprietary to MediaTek Inc Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited 1 Document Revisi...

Page 3: ...1 PCB Stack up 9 6 2 Transmission Line 10 6 2 1 50 Single ended 10 6 2 2 50 Differential ended 10 6 3 Package Information 11 6 4 Top Marking 12 7 RF Front End Circuit Design 13 7 1 RF System Overview...

Page 4: ...U Buck 1 6V Supply Output 24 8 2 3 PMU LDO 2 5V Supply Output 25 8 2 4 PMU LDO 1 6V Supply Input 25 8 2 5 PMU LDO 1 15V Supply Output 26 8 3 RTC Battery Supply 28 8 4 Power GND Checklist 30 9 Clock 31...

Page 5: ...rmation in whole or in part is strictly prohibited 3 List of Tables Table 6 1 PCB Single Setting 9 Table 6 2 PCB Layer Stack up 9 Table 8 1 MT3620 Power Rail Table 22 Table 8 2 Power Inductor QVL list...

Page 6: ...atching Circuits 16 Figure 7 7 RF Power Rails 16 Figure 7 8 RF Power Supply Capacitor Placement 17 Figure 7 9 AVDD_3V3_WF_A_TX Trace Routing Method 17 Figure 8 1 Chip Power Block Diagram 21 Figure 8 2...

Page 7: ...of which runs at up to 200MHz These subsystems were designed to support real time requirements when interfacing with a variety of on chip peripherals including UART I2C SPI I2S and ADC They are compl...

Page 8: ...i Fi MAC Wi Fi PSE Wi Fi RF SRAM Wi Fi subsystem Application processor subsystem RTC UART x 2 PWM counter UART x 2 UART SPI I2C up to x76 x12 x6 x5 ADC UART x 2 I2S x2 I O peripherals Cortex M4F I O s...

Page 9: ...e Setting 4 Layer PCB Single Setting Layer 1 signal Layer 2 ground plane unbroken Layer 3 Vdd 3 3V plane Layer 4 signal Table 6 2 PCB Layer Stack up PCB Stack Up Layer Signal Type Layer Type PCB thick...

Page 10: ...ansmission Line 6 2 1 50 Single ended 50 single ended transmission line on the top plane is in reference to the GND plane on layer 2 Figure 6 1 A 50 single ended transmission line in reference to Laye...

Page 11: ...fidential 2020 MediaTek Inc Page 11 of 40 This document contains information that is proprietary to MediaTek Inc Unauthorized reproduction or disclosure of this information in whole or in part is stri...

Page 12: ...Confidential 2020 MediaTek Inc Page 12 of 40 This document contains information that is proprietary to MediaTek Inc Unauthorized reproduction or disclosure of this information in whole or in part is...

Page 13: ...tions The first supports dual band 5GHz and 2 4GHz and includes support to transmit and receive diversity The second circuit is a simplified version that supports single band 2 4GHz and a single anten...

Page 14: ...2 4GHz Wi Fi radio transceiver The 2 4GHz Wi Fi transceiver intergrates a PA LNA and T R switch The differential pair is 50 having a matching network between 50 50 balun Figure 7 3 RF 5G 2 4G Main Pa...

Page 15: ...ure 7 4 RF Auxiliary Path Circuit 7 4 RF Component Placement 7 4 1 RF matching circuit placement 2 4GHz matching component placement Please make placement and layout of 2GHz matching network according...

Page 16: ...isclosure of this information in whole or in part is strictly prohibited Figure 7 6 Layout Placement for 2 4GHz 5GHz Matching Circuits 7 4 2 RF Power circuit placement There are two RF power rails whi...

Page 17: ...hibited Place these RF power capacitors as close as possible to the relevant pins Each pin pin pair should be decoupled with a 2 2uF or 4 7uF capacitor in parallel with a 10pF capacitor The 10pF capac...

Page 18: ...ty fast diversity Basebase softwware automatically controls switching between the main and auxilliary receive paths Transmission only occurs throug the main antenna port BBPLL RSSI Meter R cal RC cal...

Page 19: ...d will form multiple simultaneous paths between the two points This results in points in space where there are strong signals and conversely points where there are very weak signal or nulls In the cas...

Page 20: ...F traces should be as short as possible RF traces should be surrounded by a strong ground with many vias connected to the reference ground RF traces should be straight and always on the 1st layer Avoi...

Page 21: ...wer other MT3620 sub systems Through an external LC filter based on a 2 2uH inductor and a 10uF capacitor it outputs a low ripple 1 6V for the Wi Fi RF system and CLDO The CLDO generates 1 15V for the...

Page 22: ...3 3v supply 2 5V ALDO off ADC analog macro 3 2 5V ELDO off e fuse macro 3 1 6V Buck normal mode low power mode BUCK on RF and XTAL 3 1 15V CLDO normal mode low power mode CLDO on Digital core logic 3...

Page 23: ...ure of this information in whole or in part is strictly prohibited Figure 8 2 PMU Buck Circuit and Layout Placement VOUT_1V6 Inductor AVDD_3V3_Buck AVSS_3V3_Buck Cin Cap Ground Plane VIA VIA VIA VIA G...

Page 24: ...d the 10uF capacitor C38 should be close to L10 as shown in Figure 8 4 The trace width from VOUT_1V6 to C38 should be at least 0 64mm The total recommend capacitance is 10uF 1uF near VOUT_1V6 and thre...

Page 25: ...10 70 Power inductor MAMK2520T2R2M Taiyo Taiyo 2520 Approved 10 70 8 2 3 PMU LDO 2 5V Supply Output Several items should be noticed here The trace width between 1uF and VOUT_2V5 pin 79 should be 0 38m...

Page 26: ...dback sense AVDD_1V6_CLDO that need to prevent noise couple to buck feedback AVDD_1V6_CLDO trace should keep away from switching noise Figure8 7 Figure 8 7 AVDD_1V6_CLDO Input Layout AVDD_1V6_XO 9 sho...

Page 27: ...4 3uF while using internal 1 15V VCORE PMU PCB trace parasitic inductance and resistance arerecommended as follows Trace define from VOUT_1V15 to C55 Trace Resistence 20 mohm Trace Inductance 2nH Fig...

Page 28: ...onnected to the MT3620 via a Schottky diode circuit for isolation The Schottky diode circuit allows the MT3620 RTC well to be powered by the battery when the system power is not available but by the s...

Page 29: ...attery when system power is available extending battery life Figure 8 11 Battery and 3V3 Power Circuit for AVDD33_RTC Several items should be noticed here When the main 3V3 supply is present D9B preve...

Page 30: ...tion 1 Power Capacitor Design guideline 1 1 Suggestion A decoupling capacitor 0 1uF is suggested for each power pin N A 1 2 Mandatory Decoupling capacitors 0 1uF must be placed as close as possible to...

Page 31: ...mension 3225 or 2520 The MAIN_XIN pin must be connected to an external 26MHz crystal as shown in Figure 9 1 The recommended value of CL and Rd are shown in Table 9 2 Figure 9 1 XTAL Circuit Table 9 2...

Page 32: ...hm impedance in relation to layer 2 The clock trace should be as short as possible with a total trace loading of 1pF Figure 9 2 Crystal Layout Placement and Routing Showing Layer 2 Keep out Layout gui...

Page 33: ...le or in part is strictly prohibited Anti Pad Layer 1 Layer 2 Recommended Remove crystal resistor capacitor pad area on layers 1 and 3 use layer 3 as a ground reference Ground Plane must be ground ref...

Page 34: ...anced and unbalanced ports are both 50 The balun specifictions MTK recommend are in following tables No Pin Definition No Pin Definition 1 Unbalanced Port 4 Balanced Port 2 GND or DC feed RF GND 5 GND...

Page 35: ...wing table No Pin Definition No Pin Definition 1 Low Band Port 3 High Band Port 2 Common Port 4 GND Parameter MTK Spec Min Typ Max Unit Port Impedance Low Band Port impedance 50 Ohm High Band Port imp...

Page 36: ...ng table provides details of which pins are used for strapping along with their function and default state In all cases strapping pins should be pulled high or low through 4 7K resistors Function Pin...

Page 37: ...oduction or disclosure of this information in whole or in part is strictly prohibited 12 SMT Guidelines 12 1 Recommended Pad Specification The via size width and the distance between via and trace are...

Page 38: ...sure of this information in whole or in part is strictly prohibited 12 2 E pad PCB Footprint The following diagram provides details of the recommended E pad PCB footprint Figure 11 12 1 Recommended E...

Page 39: ...formation in whole or in part is strictly prohibited 12 4 Signal Pad PCB Footprint The following diagram provides details of the recommended signal pad PCB footprint Figure 11 12 3 Recommended signal...

Page 40: ...Profile Guideline The following reflow profile guideline is designed for SnAgCu lead free solder paste MTK recommend that customers follow their specific solder paste vendor s guideline and design a...

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