PCI-DAS6031 & PCI-DAS6033 User's Guide
Functional Details
CTR2 CLK signal
The CTR2 CLK signal can serve as the clock source for independent user counter 2. It can be selected through
software at the CTR2 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified.
shows the timing requirements for the CTR2 CLK signal.
Figure
4-32
Figure 4-32. CTR2 CLK signal timing
t
w-L
t
w-H
=15 ns minimum
t
w-H
t
p
=100 ns minimum
t
w-L
=25 ns minimum
CTR2 GATE signal
You can use the CTR2 GATE signal for starting and stopping the counter, saving counter contents, etc. It is
polarity programmable and is available at the CTR2 GATE pin. Fi
shows the timing requirements for
the CTR2 GATE signal.
gure 4-33
Figure 4-33. CTR2 GATE signal timing
Rising Edge Polarity
t
w
t
w
= 25 ns minimum
Falling Edge Polarity
CTR2 OUT signal
This signal is present on the CTR2 OUT pin. The CTR2 OUT signal is the output of one of the two user’s
counters in an industry-standard 82C54 chip.
For detailed information on counter operations, please refer to the data sheet on our web site at
www.measurementcomputing.com/PDFmanuals/82C54.pdf
.
Figure 4-34
Figure 4-34. CTR2 OUT signal timing
shows the timing of the CTR1 OUT signal for mode 0 and for mode 2.
CTR2 CLK
TC
CTR2 OUT (Mode 2)
CTR2 OUT (Mode 0)
4-17
Summary of Contents for PCI-DAS6031
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