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Chapter 5

Calibrating the PCI-DAS6031 and PCI-DAS6033

Introduction

You should calibrate the board (using the

Insta

Cal utility) after the board has fully warmed up. The

recommended warm-up time is 15 minutes. For best results, calibrate the board immediately before making
critical measurements. The high resolution analog components on the board are somewhat sensitive to
temperature. Pre-measurement calibration ensures that your board is operating at optimum calibration values.

Calibration theory

Analog inputs are calibrated for offset and gain. Offset calibration for the analog inputs is performed directly on
the input amplifier (PGIA) with coarse and fine trim DACs acting on the amplifier.

For input gain calibration, a precision calibration reference is used with coarse and fine trim DACs acting on the
ADC (see Figure 5-1).

Trim DAC

Coarse

Trim DAC

Fine

Gain

Adjust

PGIA

Analog In

A/D

Trim DAC

Coarse

Trim DAC

Fine

Pre-Gain

Offset

Trim DAC

Coarse

Trim DAC

Fine

Post-Gain

Offset

Figure 5-1. Analog input calibration - basic elements

5-1

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Summary of Contents for PCI-DAS6031

Page 1: ...i ...

Page 2: ...PCI DAS6031 and PCI DAS6033 Analog and Digital I O Boards User s Guide Document Revision 5 May 2006 Copyright 2006 Measurement Computing Corporation ...

Page 3: ... that is damaged even due to misuse for only 50 of the current list price I O boards face some tough operating conditions some more severe than the boards are designed to withstand When a board becomes damaged just return the unit with an order for its replacement at only 50 of the current list price We don t need to profit from your misfortune By the way we honor this warranty for any manufacture...

Page 4: ...e is granted by implication or otherwise under any patent or copyrights of Measurement Computing Corporation All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without the prior written permission of Measurement Computing Corporation Notice Measurement Co...

Page 5: ... ended input mode 2 3 Non referenced single ended input mode 2 3 DAQ Sync configuration 2 4 Connecting the board for I O operations 2 4 Connectors cables main I O connector 2 4 Pinout main I O connector 2 5 DAQ Sync connector and pinout 2 8 Field wiring signal termination and conditioning 2 8 Chapter 3 Programming and Developing Applications 3 1 Programming languages 3 1 Packaged applications prog...

Page 6: ...I DAS6033 5 1 Introduction 5 1 Calibration theory 5 1 Chapter 6 Specifications 6 1 Analog input 6 1 Accuracy 6 2 Settling time 6 3 Parametrics 6 4 Noise performance 6 4 Analog output PCI DAS6031 only 6 5 Analog output pacing and triggering 6 6 Analog trigger 6 6 Analog input output calibration 6 7 Digital input output 6 7 Interrupts 6 7 Counters 6 8 Configurable AUXIN 5 0 AUXOUT 2 0 external trigg...

Page 7: ... topic titles and to emphasize a word or phrase For example The InstaCal installation procedure is explained in the Quick Start Guide Never touch the exposed pins or circuit connections on the board Where to find more information The following electronic documents provide helpful information relevant to the operation of the PCI DAS6031 and PCI DAS6033 MCC s Specifications PCI DAS6031 and PCI DAS60...

Page 8: ...3 provide triggering and synchronization capability There are five trigger strobes and a synchronizing clock provided on a 14 pin header The DAQ Sync signals use dedicated pins Only the direction can be set Refer to Chapter 2 Installing the Board and Chapter 6 Specifications for more information on these signals Interrupts can be generated by up to seven ADC sources and four DAC sources Interrupt ...

Page 9: ...ription of the software you received with your PCI DAS6031 and PCI DAS6033 and information regarding installation of that software Please read this booklet completely before installing any software or hardware Optional components If you ordered any of the following products with your board they should be included with your shipment Cables C100HD50 x C100MMS x CDS 14 x Signal termination and condit...

Page 10: ...all your board follow the steps below Install the MCC DAQ software before you install your board The driver needed to run your board is installed with the MCC DAQ software Therefore you need to install the MCC DAQ software before you install your board Refer to the Quick Start Guide for instructions on installing the software 1 2 3 Turn your computer off open it up and insert your board into an av...

Page 11: ...ns in noisy environments or when the signal source is referenced to a potential other than PC ground Single ended input mode When all channels are configured for single ended input mode 64 analog input channels are available In this mode the input signal is referenced to the board s signal ground LLGND The input signal is delivered through two wires The wire carrying the signal to be measured conn...

Page 12: ...AS6000 series boards A CDS 14 3 cable is shown in Figure 2 3 By default all DAQ Sync connectors are configured as inputs slave mode In order to be useful use software to configure one board as the master and to define the signal sources of the slave boards Refer to DAQ Sync signals on page 4 2 for more information Connecting the board for I O operations Connectors cables main I O connector Table 2...

Page 13: ...0 30 CH13 IN LO CH29 IN HI 79 29 CH13 IN HI CH28 IN LO 78 28 CH12 IN LO CH28 IN HI 77 27 CH12 IN HI CH27 IN LO 76 26 CH11 IN LO CH27 IN HI 75 25 CH11 IN HI CH26 IN LO 74 24 CH10 IN LO CH26 IN HI 73 23 CH10 IN HI CH25 IN LO 72 22 CH9 IN LO CH25 IN HI 71 21 CH9 IN HI CH24 IN LO 70 20 CH8 IN LO CH24 IN HI 69 19 CH8 IN HI LLGND 68 18 LLGND CH23 IN LO 67 17 CH7 IN LO CH23 IN HI 66 16 CH7 IN HI CH22 IN ...

Page 14: ...N CH31 IN 83 33 CH15 IN CH62 IN 82 32 CH46 IN CH30 IN 81 31 CH14 IN CH61 IN 80 30 CH45 IN CH29 IN 79 29 CH13 IN CH60 IN 78 28 CH44 IN CH28 IN 77 27 CH12 IN CH59 IN 76 26 CH43 IN CH27 IN 75 25 CH11 IN CH58 IN 74 24 CH42 IN CH26 IN 73 23 CH10 IN CH57 IN 72 22 CH41 IN CH25 IN 71 21 CH9 IN CH56 IN 70 20 CH40 IN CH24 IN 69 19 CH8 IN LLGND 68 18 LLGND CH55 IN 67 17 CH39 IN CH23 IN 66 16 CH7 IN CH54 IN 6...

Page 15: ... is stamped Pins 1 50 Pins 1 50 are on the long side of the D connector Pins 51 100 are on the short side of the D connector Key Key The red stripe identifies pin 1 The red stripe identifies pin 51 Strain relief is Stamped Pins 51 100 Figure 2 1 C100HD50 x cable connections 100 50 51 1 100 50 51 1 Figure 2 2 C100MMS x cable 2 7 ...

Page 16: ...on our web site at www mccdaq com cbicatalog cbiproduct asp dept 5Fid 128 pf 5Fid 710 BNC 16SE 16 channel single ended BNC connector box Details are available at www mccdaq com cbicatalog cbiproduct asp dept 5Fid 101 pf 5Fid 713 BNC 16DI 8 channel differential BNC connector box Details are available at www mccdaq com cbicatalog cbiproduct asp dept 5Fid 101 pf 5Fid 714 CIO MINI50 50 pin screw termi...

Page 17: ...rivers for the board please fax or e mail the package name and the revision number from the install disks We will research the package for you and advise how to obtain drivers Some application drivers are included with the Universal Library package but not with the application package If you have purchased an application package directly from the software vendor you may need to purchase our Univer...

Page 18: ... the memory bus carries A D and D A related data and commands There are three buffer memories provided on the memory bus The queue buffer 8K configuration memory stores programmed channel numbers gains and offsets The ADC buffer 8K FIFO First In First Out temporarily stores scanned and converted analog inputs The DAC 16K buffer stores data to be output as analog waveforms Auxiliary input output in...

Page 19: ... A update pulse default CTR2 CLK CTR2 clock source A D START TRIGGER ADC Start Trigger Out A D STOP TRIGGER ADC Stop Trigger Out A D PACER GATE External ADC gate AUXOUT 2 0 sources SW selectable D A START TRIGGER DAC Start Trigger Out AUXIN0 A D CONVERT AUXIN1 A D START TRIGGER AUXIN2 A D STOP TRIGGER AUXIN3 D A UPDATE AUXIN4 D A START TRIGGER AUXIN5 A D PACER GATE AUXOUT0 D A UPDATE AUXOUT1 A D C...

Page 20: ...time base used to derive all board timing and control The master provides this clock to the slave boards so that all boards in the DAQ Sync enabled system are timed from the same clock MEMORY BUS ADC 16 BIT Mux Gain Analog In D Q EOC 16 HOLDING REGISTER 40 MHz A D PACER OUT SCANCLK D A PACER OUT A D CONVERT A D START TRIGGER D A UPDATE D A START TRIGGER A D PACER GATE LOCAL BUS PCI BUS 5V 32 BIT 3...

Page 21: ...in for the SCANCLK signal is AUXOUT2 but any of the AUXOUT pins may be programmed as a SCANCLK output CONVERT SCANCLK td td tw td 50 ns tw 400 ns Figure 4 2 SCANCLK signal timing A D START TRIGGER signal Use the A D START TRIGGER signal for conventional triggering when you only need to acquire data after a trigger event shows the A D START TRIGGER signal timing for a conventionally triggered acqui...

Page 22: ...ered data acquisition continually acquires data into a circular buffer until a specified number of samples have been collected after the trigger event illustrates a typical pre triggered DAQ sequence Figure 4 6 Figure 4 6 Pre triggered data acquisition example A D Start Trigger Start Scan Convert 3 2 1 0 3 2 1 0 3 2 1 A D Stop Trigger Scan Counter Don t care The A D STOP TRIGGER signal signifies w...

Page 23: ...IGGER input signal timing Figure 4 8 Figure 4 8 A D STOP TRIGGER output signal timing Rising Edge Polarity tw tw 37 5 ns minimum Falling Edge Polarity tw tw 50 ns STARTSCAN signal The STARTSCAN output signal indicates when a scan of channels has been initiated You can program this signal to be available at any of the AUXOUT pins The STARTSCAN output signal is a 50 ns wide pulse the leading edge of...

Page 24: ... Sync DS A D CONVERT input and as an output to any of the AUXOUT pins When used as an input the polarity is software selectable The A D CONVERT signal starts an acquisition on the selected edge The selected edge either rising of falling of the convert pulses must be separated by a minimum of 10 µs to remain within the 100 kS s conversion rate specification Refer to and for the relationship of A D ...

Page 25: ...ny AUXIN pin can be set programmatically as the source for this signal The polarity is programmable The maximum frequency for the A D EXTERNAL TIME BASE signal is 20 MHz The minimum pulse width is 23 ns high or low There is no minimum frequency specification Figure 4 13 Figure 4 13 A D EXTERNAL TIME BASE signal timing shows the timing specifications for the A D EXTERNAL TIME BASE signal tw tw 23 n...

Page 26: ... V 12 bit DACs are used to set the HI and LO levels for the threshold s The threshold resolution in this mode is 4 88 mV per step Figure 4 15 Figure 4 15 ATRIG circuit Caution Remove all analog inputs before configuring this pin as a digital input Any voltage levels above 15 V in this configuration may cause damage to the product The second possible analog trigger source is the post gain version o...

Page 27: ...RESH_HI This mode is non retriggerable Thresh_HI 2 2 1 0 1 Trigger Acquired Data 2 2 1 0 1 Figure 4 16 Trigger positive slope Trigger Below The acquisition will begin when ATRIG signal first goes below the THRESH_LO level This mode is non retriggerable Thresh_LO 2 2 1 0 1 Trigger Acquired Data 2 2 1 0 1 Figure 4 17 Trigger negative slope 4 10 ...

Page 28: ...RESH_HI level This is a level sensitive gating mode Trigger Result 2 2 1 0 1 Thresh_HI 2 1 0 1 2 2 1 0 1 Figure 4 18 Gate Above Gate Below Data acquisition is enabled whenever ATRIG goes below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal goes above the THRESH_LO level This is a level sensitive gating mode Trigger Acquired Data 2 2 1 0 1 Thresh_LO 1 0 1 2 Figure 4 19 Gate ...

Page 29: ... level sensitive gating mode Trigger Acquired Data 2 2 1 0 1 Thresh_HI 2 1 0 1 Thresh_LO Figure 4 20 Gate Negative Hysteresis Gate Positive Hysteresis Data acquisition is enabled whenever ATRIG goes below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal goes above the THRESH_HI level The hysteresis level is set by THRESH_HI This is a level sensitive gating mode Trigger Acquir...

Page 30: ... sensitive gating mode Thresh_HI 2 2 1 0 1 Trigger Acquired Data 2 2 1 0 1 Thresh_LO Figure 4 22 Gate Inside Window Gate Outside Window Data acquisition is enabled whenever ATRIG is above the THRESH_HI level or below the THRESH_LO level Acquisition is suspended whenever the ATRIG signal is between the THRESH_HI and THRESH_LO levels This is a level sensitive gating mode Thresh_HI 2 2 1 0 1 Trigger ...

Page 31: ...s an output to monitor the trigger that initiates waveform generation The output is an active high pulse having a width of 50 ns Figure 4 24 Figure 4 24 D A START TRIGGER input signal timing and show the input and output timing requirements for the D A START TRIGGER signal Figure 4 25 Figure 4 25 D A START TRIGGER output signal timing Rising Edge Polarity tw tw 37 5 ns minimum Falling Edge Polarit...

Page 32: ... DAC pacer circuit rather than using the internal time base Any AUXIN pin can be set programmatically as the source for this signal The polarity is programmable The maximum frequency for the D A EXTERNAL TIME BASE signal is 20 MHz The minimum pulse width is 23 ns high or low There is no minimum frequency specification Figure 4 28 Figure 4 28 D A EXTERNAL TIME BASE signal timing shows the timing re...

Page 33: ...gnal for starting and stopping the counter saving counter contents etc It is polarity programmable and is available at the CTR1 GATE pin Figure 4 30 Figure 4 30 CTR1 GATE signal timing shows the minimum timing requirements for the CTR1 GATE signal Rising Edge Polarity tw tw 25 ns minimum Falling Edge Polarity CTR1 OUT signal This signal is present on the CTR1 OUT pin The CTR1 OUT signal is the out...

Page 34: ... GATE signal for starting and stopping the counter saving counter contents etc It is polarity programmable and is available at the CTR2 GATE pin Fi shows the timing requirements for the CTR2 GATE signal gure 4 33 Figure 4 33 CTR2 GATE signal timing Rising Edge Polarity tw tw 25 ns minimum Falling Edge Polarity CTR2 OUT signal This signal is present on the CTR2 OUT pin The CTR2 OUT signal is the ou...

Page 35: ... that your board is operating at optimum calibration values Calibration theory Analog inputs are calibrated for offset and gain Offset calibration for the analog inputs is performed directly on the input amplifier PGIA with coarse and fine trim DACs acting on the amplifier For input gain calibration a precision calibration reference is used with coarse and fine trim DACs acting on the ADC see Figu...

Page 36: ...utput components A trim DAC is used to adjust the gain of the DAC A separate DAC is used to adjust offset on the final output amplifier The calibration circuits are duplicated for both analog outputs see Figure 5 2 Figure 5 2 Analog output calibration basic elements Trim DAC Ref D A Gain Adjust Analog Out Trim DAC Offset Adjust 5 2 ...

Page 37: ...ble option burst rate 10 µS External digital A D GATE A D gate sources External analog ATRIG input CH0 IN through CH63 IN External digital Programmable active high or active low level or edge A D gating modes External analog Refer to the Analog Trigger section on page 6 External digital A D START TRIGGER A D STOP TRIGGER A D trigger sources External analog ATRIG input CH0 IN through CH63 IN Extern...

Page 38: ...00 mV 38 67 LSB Table 3 Absolute Accuracy Components All values are Noise Quantization µV Range of Reading Offset µV Single Pt Averaged1 Temp Drift ºC Absolute Accuracy at FS mV 10 V 0 0061 479 2 634 1 54 9 0 0001 1 147 5 V 0 0361 243 6 317 1 27 5 0 0006 2 077 2 V 0 0361 102 2 126 8 11 0 0 0006 0 836 1 V 0 0361 55 1 63 4 5 5 0 0006 0 422 500 mV 0 0361 31 6 36 8 3 2 0 0006 0 215 200 mV 0 0411 17 4 ...

Page 39: ...d for a channel to settle to within a specified accuracy in response to a full scale FS step Two channels are scanned at the specified rate A FS DC signal is presented to Channel 1 a FS DC signal is presented to Channel 0 Table 6 Settling tme specifications Condition Range 0 00076 0 5 LSB 0 0015 1 LSB 0 0061 4 LSB 0 012 8 LSB 10 V 50 µS max 25 µS max 10 µS max 5 µS typ 5 V 50 µS max 25 µS max 10 µ...

Page 40: ... 100 pA Absolute maximum input voltage 25 V power on 15 V power off Protected inputs CH 63 0 IN AISENSE Adjacent channels 75 dB Crosstalk All other channels 90 dB Noise performance Table 8 Table 8 Analog input noise performance specifications summarizes the noise performance for the PCI DAS6031 and PCI DAS6033 Noise distribution is determined by gathering 50 k samples with inputs tied to ground at...

Page 41: ... Ohms max Power up and reset DACs cleared to 0 volts 20 mV max Table 10 Analog output absolute accuracy specifications Table 10 Range Absolute Accuracy 10 V 4 7 LSB 0 to 10 V 7 9 LSB Table 11 Absolute accuracy components All values are Range of Reading Offset µV Temp Drift ºC Absolute Accuracy at FS mV 10 V 0 0062 813 0 0001 1 430 0 to 10 V 0 0062 584 0 0001 1 201 Each PCI DAS6031 is tested at the...

Page 42: ...ng edge DAC triggering modes External analog Software configurable for positive or negative slope DAC pacer Out Available at user connector D A PACER OUT RAM buffer Size 16 K samples DMA Programmed I O Data transfer Update DACs individually or simultaneously software selectable DMA modes Demand or non demand using scatter gather Waveform generation throughput 100 kS s max per channel 2 channels si...

Page 43: ...ge IOL 32 mA 0 55 V max 0 22 V typ Data transfer Programmed I O Power up reset state Input mode high impedance Interrupts Table 17 Interrupt specifications Interrupts PCI INTA mapped to IRQn via PCI BIOS at boot time Interrupt enable Programmable through PLX9080 DAQ_ACTIVE Interrupt is generated when a DAQ sequence is active DAQ_STOP Interrupt is generated when A D Stop Trigger In is detected DAQ_...

Page 44: ...kHz External connector CTRn CLK Internal 10 MHz clock source stability 50 ppm Counter n gate Available at connector CTRn GATE Counter n output Available at connector CTRn OUT Clock input frequency 10 MHz max High pulse width clock input 15 ns min Low pulse width clock input 25 ns min Gate width high 25 ns min Gate width low 25 ns min Input low voltage 0 8 V max Input high voltage 2 0V min Output l...

Page 45: ... A UPDATE DAC update strobe D A TIMEBASE IN External DAC pacer time base AUXOUT 2 0 sources SW selectable STARTSCAN A pulse indicating start of conversion SSH Active signal that terminates at the start of the last conversion in a scan A D STOP Indicates end of scan A D CONVERT ADC convert pulse SCANCLK Delayed version of ADC convert CTR1 CLK CTR1 clock source D A UPDATE D A update pulse CTR2 CLK C...

Page 46: ...ER DS A D CONVERT DS D A UPDATE DS D A START TRIGGER DAQ Sync signals SYNC CLK Power consumption Table 21 Power consumption specifications 5 V PCI DAS6031 32 1 3 A typical 1 5 A max Does not include power consumed through the I O connector 5 V available at I O connector 1 A max protected with a resettable fuse Environmental Table 22 Environmental specifications Operating temperature range 0 to 55 ...

Page 47: ...OP TRIGGER 4 GND 5 DS A D CONVERT 6 GND 7 DS D A UPDATE 8 GND 9 DS D A START TRIGGER 10 GND 11 RESERVED 12 GND 13 SYNC CLK 14 GND Main connector and pin out Table 26 Main connector specifications Connector type Shielded SCSI 100 D type C100HD50 x unshielded ribbon cable x 3 or 6 feet Compatible cables C100MMS x shielded round cable x 1 2 or 3 meters Compatible accessory products with C100HD50 x ca...

Page 48: ... HI 71 CH25 IN HI 22 CH9 IN LO 72 CH25 IN LO 23 CH10 IN HI 73 CH26 IN HI 24 CH10 IN LO 74 CH26 IN LO 25 CH11 IN HI 75 CH27 IN HI 26 CH11 IN LO 76 CH27 IN LO 27 CH12 IN HI 77 CH28 IN HI 28 CH12 IN LO 78 CH28 IN LO 29 CH13 IN HI 79 CH29 IN HI 30 CH13 IN LO 80 CH29 IN LO 31 CH14 IN HI 81 CH30 IN HI 32 CH14 IN LO 82 CH30 IN LO 33 CH15 IN HI 83 CH31 IN HI 34 CH15 IN LO 84 CH31 IN LO 35 AISENSE 85 DIO0 ...

Page 49: ... IN 22 CH41 IN 72 CH57 IN 23 CH10 IN 73 CH26 IN 24 CH42 IN 74 CH58 IN 25 CH11 IN 75 CH27 IN 26 CH43 IN 76 CH59 IN 27 CH12 IN 77 CH28 IN 28 CH44 IN 78 CH60 IN 29 CH13 IN 79 CH29 IN 30 CH45 IN 80 CH61 IN 31 CH14 IN 81 CH30 IN 32 CH46 IN 82 CH62 IN 33 CH15 IN 83 CH31 IN 34 CH47 IN 84 CH63 IN 35 AISENSE 85 DIO0 36 D A OUT 0 86 DIO1 37 D A GND 87 DIO2 38 D A OUT1 88 DIO3 39 PC 5 V 89 DIO4 40 AUXOUT0 D ...

Page 50: ...ducted emissions Immunity EN61326 Annex A IEC 1000 4 2 1995 Electrostatic Discharge immunity Criteria C IEC 1000 4 3 1995 Radiated Electromagnetic Field immunity Criteria A IEC 1000 4 4 1995 Electric Fast Transient Burst immunity Criteria B IEC 1000 4 5 1995 Surge immunity Criteria A IEC 1000 4 6 1996 Radio Frequency Common Mode immunity Criteria A IEC 1000 4 8 1994 Magnetic Field immunity Criteri...

Page 51: ...ducted emissions Immunity EN61326 Annex A IEC 1000 4 2 1995 Electrostatic Discharge immunity Criteria C IEC 1000 4 3 1995 Radiated Electromagnetic Field immunity Criteria A IEC 1000 4 4 1995 Electric Fast Transient Burst immunity Criteria B IEC 1000 4 5 1995 Surge immunity Criteria A IEC 1000 4 6 1996 Radio Frequency Common Mode immunity Criteria A IEC 1000 4 8 1994 Magnetic Field immunity Criteri...

Page 52: ...Measurement Computing Corporation 10 Commerce Way Suite 1008 Norton Massachusetts 02766 508 946 5100 Fax 508 946 9500 E mail info mccdaq com www mccdaq com ...

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