Table 6-2. Interrupt Coding
7
1
1
1
6
0
1
1
5
1
0
1
4
0
0
1
3
1
1
0
2
0
1
0
None
1
0
0
None
0
0
0
INTERRUPT LEVEL
IR0
IR1
IR2
DMA = 1, DMA transfers are enabled.
DMA = 0, DMA transfers are disabled.
Note that this bit only allows the CIO-DAS1400 to assert a DMA request to the PC on the DMA request level selected by the DMA
switch on the CIO-DAS1400. Before this bit is set to 1, the PC's 8237 (or appropriate) DMA controller chip must be set up.
TS1 & TS0 control the source of the A/D start conversion trigger according to table 6-3 below.
Table 6-3. Trigger Source TS0 and TS1 Control Codes
Start on Pacer Clock Pulse (CTR 2 OUT, no external access)
1
1
Start on rising edge (Digital input 0, Pin 25)
0
1
Software triggered A/D only
X
0
TS0
TS1
6.2.7
Pacer Clock Control Register
BASE A A hex
TRIG0
CTR0
X
X
BL0
BL1
BL2
BL3
0
1
2
3
4
5
6
7
This register is write-only.
BL3 - BL0 = BURST LENGTH. Nibble determines number of conversions per trigger when in burst mode. One to sixteen samples
(single ended) or eight samples (differential) in a burst. When the CIO-DAS1400 is not in burst mode these bits have no function.
CTR0 = 1. When CTR0 = 1, an onboard 100KHz clock signal is ANDed with the COUNTER 0 CLOCK INPUT (pin 21). A high on
pin 21 will allow pulses from the onboard source into the 8254 Counter 0 input. (This input has a pull-up resistor on it, so no
connection is necessary to use the onboard clock as a pacer clock.
CTR0 = 0. When CTR0 = 0, the input to 8254 Counter 0 is entirely dependent on pulses at pin 21, COUNTER 0 CLOCK INPUT.
TRIG0 = 1. When TRIG0 = 1 external gating of the pacer clock at pin 25 is enabled. Pin 25 going high will start A/D conversions.
The input at pin 25 is connected to a pull-up resistor and will remain high unless pulled low externally.
TRIG0 = 0. When TRIG0 = 0, the gating of the pacer clock at pin 25 is disabled. The gates of counter 1 & 2 are held high, preventing
external control of the pacer gate.
-16-
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