6.2.2
A/D Data & Channel Registers (CIO-DAS1402/16)
BASE ADDRESS
A/D 0
LSB
A/D 1
A/D 2
A/D 3
A/D 4
A/D 5
A/D 6
A/D 7
0
1
2
3
4
5
6
7
This register is read/write.
READ
On read, it contains the least significant eight digits of the analog input data.
These eight bits of analog input data are combined with the eight bits of analog input data in BASE + 1, forming a complete 16-bit
number. The data is in the format 0 = minus full scale. 65,535 = +FS.
WRITE
Writing any data to the register causes an immediate A/D conversion.
BASE A1
A/D 8
A/D 9
A/D 10
A/D 11
A/D 12
A/D 13
A/D 14
A/D 15
MSB
0
1
2
3
4
5
6
7
This register is read-only. On read, the most significant A/D byte is read.
6.2.3
Channel MUX Scan Limits Register
BASE A2
CH L0
CH L1
CH L2
CH L3
CH H0
CH H1
CH H2
CH H3
0
1
2
3
4
5
6
7
This register is read and write.
READ
The current channel scan limits are read as one byte. The high channel number scan limit is in the most significant four bits. The low
channel scan limit is in the least significant four bits.
WRITE
The channel scan limits desired are written as one byte. The high channel number scan limit is in the most significant four bits. The
low channel scan limit is in the least significant four bits.
NOTE
Every write to this register sets the current A/D channel MUX setting to the number in bits 0-3 and resets the FIFO. See BASE + 8.
6.2.4
Four-Bit Digital I/O Registers
BASE A3 (when read)
DI0, TRIG
DI1
DI2, CTR0 GATE
DI3
0
0
1
1
0
1
2
3
4
5
6
7
READ
The signals present at the inputs are read as one byte, the most significant four bits of which are always zero. Pins 25 (digital input 0)
and 24 (digital input 2) digital inputs have two functions each.
The TRIG function of digital input 0 may be used to hold off the first sample of an A/D set by holding it low (0V) until you are ready
to take samples, which are then paced by the 8254. It can also be used as the source of an external start conversion pulse,
synchronizing A/D conversions to some external event.
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