6.2.9
Pacer Clock Data & Control Registers
8254 COUNTER 0 DATA
BASE AC hex
D1
D2
D3
D4
D5
D6
D7
D8
0
1
2
3
4
5
6
7
8254 COUNTER 1 DATA
BASE AD hex
D1
D2
D3
D4
D5
D6
D7
D8
0
1
2
3
4
5
6
7
8254 COUNTER 2 DATA
BASE AE hex
D1
D2
D3
D4
D5
D6
D7
D8
0
1
2
3
4
5
6
7
The three 8254 counter/timer data registers are read/write. Because each counter can count as high as 64,535, it is clear that loading or
reading the counter data is a multi-step process. The operation of the 8254 is explained in Intel’s 8254 data sheet.
8254 COUNTER CONTROL
BASE AF hex
D1
D2
D3
D4
D5
D6
D7
D8
0
1
2
3
4
5
6
7
This register controls the operation and loading/reading of the counters. The configuration of the 8254 codes which control the 8254
chip is explained in the Intel 8254 data sheet.
6.2.10 Convert Disable Register
BASE A404 hex
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
WRITE ONLY. Writing a 0 to this register enables triggering of the A/D converter if the DAS1400 mode is enabled. On power-up or
reset this register is reset to conversion triggers enabled. Writing a 40 hex to this register disables A/D conversions.
6.2.11 Burst Mode Enable Register
BASE A405 hex
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
WRITE ONLY. Burst mode enable. Writing 40 hex to this register enables the burst trigger. Writing 0 to this register disables burst
trigger. On power-up or reset the burst trigger is disabled.
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