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INTERFACE COMMANDS

7 – 4

Set Multiple Mode

Set Multiple Mode

Set Multiple Mode

Set Multiple Mode

Set Multiple Mode

Enables the controller to perform Read and Write Multiple operations, and establishes the block count for
these commands. Before issuing this command, the Sector Count register should be loaded with the number
of sectors per block. The drives support block sizes of 2, 4, 8 and 16 sectors.

When this command is received, the controller sets BSY and examines the Sector Count register contents. If
they contain a valid and supported block count value, that value is loaded for all subsequent Read and Write
Multiple commands, and execution of those commands is enabled. An invalid and unsupported block count
in the register results in an Aborted Command error and disallows Read Multiple and Write Multiple
commands.

Write Commands

Write Commands

Write Commands

Write Commands

Write Commands

Write Sector(s)

Write Sector(s)

Write Sector(s)

Write Sector(s)

Write Sector(s)

Writes from 1 to 256 sectors, beginning at a sector specified in the Command Block. (A sector count of 0
requests 256 sectors.)

When the Command register is written, the drive sets the DRQ bit and waits for the host to fill the sector
buffer with the data to be written. An interrupt is not generated to start the first buffer fill operation.

Once the buffer is full, the drive resets DRQ, sets BSY, and begins command execution. If the drive is not
already on the desired track, an implied seek is performed.

The data loaded in the buffer is written to the data field of the sector, followed by the ECC bytes. Upon
command completion, the Command Block registers contain the cylinder, head and sector number of the
last sector written. The next time the buffer is ready to be filled during back-to-back Write Sector
commands, DRQ is set and an interrupt is generated.

After the host fills the buffer, DRQ is reset and BSY is set. If an error occurs, Write Sector operations
terminate at the sector containing the error.

The Command Block registers then contain the numbers of the cylinder, head and sector where the error
occurred. The host may read the Command Block to determine the nature of that error, and on which
sector it happened. A Write Long may be executed by setting the Long bit in the command code. The
Write Long command writes the data and the ECC bytes directly from the sector buffer; the drive itself does
not generate the ECC bytes. Restrict Write Long commands to PIO Mode 0.

Write Verify Sector(s)

Write Verify Sector(s)

Write Verify Sector(s)

Write Verify Sector(s)

Write Verify Sector(s)

Identical to the Write Sector(s) command, except that the requested sectors are verified immediately after
being written. The verify operation reads (without transferring), and checks for data errors. Any errors
encountered during this operation are reported.

Write Sector Buffer

Write Sector Buffer

Write Sector Buffer

Write Sector Buffer

Write Sector Buffer

Allows the host to overwrite the contents of the drive’s sector buffer with a selected data pattern. When this
command is received, the drive:

1. Sets BSY,
2. Sets up the sector buffer for a write operation,
3. Sets DRQ,
4. Resets BSY and
5. Generates an interrupt.

The host may then write up to 256 words of data to the buffer. A disk write task begins to store the host
data to disk. Host write commands continue to be accepted and data transferred to the buffer until either
the write command stack is full or the data buffer is full. The drive may reorder write commands to optimize
drive throughput.

Summary of Contents for 2R010H1

Page 1: ...ribed in this publication at any time and without notice Copyright 2001 Maxtor Corporation All rights reserved Maxtor MaxFax and No Quibble Service are registered trademarks of Maxtor Corporation Othe...

Page 2: ...tic discharge ESD precautions includingpersonnelandequipmentgrounding Stand alonedrivesare sensitive to ESD damage 2 2 2 2 2 BEFORE removing drives from their packing material allow them to reach room...

Page 3: ...2 2 Read Write Multiple Mode 2 2 Ultra ATA Mode 5 2 2 Multi word DMA EISA Type B Mode 2 2 2 Sector Address Translation 2 2 Logical Block Addressing 2 3 Defect Management Zone 2 3 On the Fly Hardware E...

Page 4: ...EMC EMI 3 5 EMC Compliance 3 5 Canadian Emissions Statement 3 5 Safety Regulatory Compliance 3 5 Section 4 Section 4 Section 4 Section 4 Section 4 Handling and Installation Handling and Installation H...

Page 5: ...6 2 Sector Number Register 6 2 Cylinder Number Registers 6 2 Device Head Register 6 2 Status Register 6 2 Command Register 6 3 Read Commands 6 3 Write Commands 6 3 Mode Set Check Commands 6 3 Power Mo...

Page 6: ...e Immediate 7 8 Standby 7 8 Idle 7 8 Check Power Mode 7 8 Set Sleep Mode 7 8 Default Power on Condition 7 9 Initialization Commands 7 10 Identify Drive 7 10 Initialize Drive Parameters 7 13 Seek Forma...

Page 7: ...a Transfer to from Device 5 3 5 3 Multi word DMA Data Transfer 5 4 5 4 Initiating an Ultra DMA Data In Burst 5 5 5 5 Sustained Ultra DMA Data In Burst 5 6 5 6 Host Pausing an Ultra DMA Data In Burst 5...

Page 8: ...puts you in touch with either technical support or customer service We ll provide you the information you need quickly accurately and in the form you prefer a fax a downloaded file or a conversation...

Page 9: ...ons Signal Conventions Signal Conventions Signal Conventions Signal Conventions Signal names are shown in all uppercase type All signals are either high active or low active signals A dash character a...

Page 10: ...n allow up to four disks in a 3 5 inch package Key Features Key Features Key Features Key Features Key Features ANSI ATA 5 compliant PIO Mode 5 interface Enhanced IDE Supports Ultra DMA Mode 5 for up...

Page 11: ...e 2 Multi word DMA EISA Type B Mode 2 Multi word DMA EISA Type B Mode 2 Supports multi word Direct Memory Access DMA EISA Type B mode transfers Sector Address Translation Sector Address Translation Se...

Page 12: ...mentation Buffer Segmentation Buffer Segmentation Buffer Segmentation The data buffer is organized into two segments the data buffer and the micro controller scratch pad The data buffer is dynamically...

Page 13: ...ead write heads provides up to eight head selection depending on the model read pre amplification and write drive circuitry Read Write Heads and Media Read Write Heads and Media Read Write Heads and M...

Page 14: ...accessed via a common interface cable using the same range of I O addresses The drives are jumpered as device 0 or 1 Master Slave and are selected by the drive select bit in the Device Head register...

Page 15: ...1 Areal Density Gbits in2 max 22 5 Trac k Density tpi 46 000 Recording Density kbpi 391 to 489 Bytes per Sector Block 512 Sectors per Track 572 to 836 Sec tors per Drive 29 297 520 20 011 824 MODELS 2...

Page 16: ...icalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions PARAMETER VALUE Height m ax mm 17 5 Width typical mm 101 6 Length m ax mm 146 6 Weight m ax kg 0 453 Figure3...

Page 17: ...Sleep Sleep Sleep Sleep Sleep This is the lowest power state with the interface set to inactive A software or hardware reset is required to return the drive to the Standby state EPA Energy Star Compli...

Page 18: ...dicates the average minimum cycles for reliable load unload function Data Reliability Data Reliability Data Reliability Data Reliability Data Reliability 1 per 10E15 bits read Data errors non recovera...

Page 19: ...led in a typical personal computer Maxtor recommends that testing and analysis for EMC compliance be performed with the disk mechanism installed within the user s end use application Canadian Emission...

Page 20: ...baseplate Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD Electro StaticDischarge ESD To avoid some of the problems associated with ESD...

Page 21: ...Inspect the shipping container for evidence of damage in transit Notify the carrier immediately in case of damage to the shipping container As they are removed inspect drives for evidence of shipping...

Page 22: ...ded Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration The Maxtor hard drive design allo...

Page 23: ...r than 8 4 GB Pentium class processor Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Drives less...

Page 24: ...the Maxtor drive This connector is keyed and will only fit one way Check all other cable connections before you power up Striped colored edge is pin 1 AfterattachingtheIDEinterfacecableandthe powercab...

Page 25: ...accommodate a cable connection maximum cable length 18 inches Figure5 1 DataConnector PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PinDescriptionSummary PIN...

Page 26: ...to insert wait states into host I O cycles DMA ready during UltraDMA data out bursts Data strobe during UltraDMA data in bursts CSEL 28 Cable Select Used for Master Slave selection via cable Requires...

Page 27: ...s 30 ns 20 ns t4 DIOW data hold min 30 ns 20 ns 15 ns 10 ns 10 ns t5 DIOR data setup min 50 ns 35 ns 20 ns 20 ns 20 ns t6 DIOW data hold min 5 ns 5 ns 5 ns 5 ns 5 ns t6Z DIOR data tristate max 30 ns 3...

Page 28: ...ld min 5 ns 5 ns 5 ns tG DIOR DIOW data setup min 100 ns 30 ns 20 ns tH DIOW data hold min 20 ns 15 ns 10 ns tI DMACK to DIOR DIOW setup min 0 0 0 tJ DIOR DIOW to DMACK hold min 20 ns 5 ns 5 ns tKr DI...

Page 29: ...UI Unlimited interlock time 0 0 0 0 0 0 tAZ Maximum time allowed for outputs to release 10 10 10 10 10 10 tZAH Minimum delay time required for output drivers turning on from released state 20 20 20 20...

Page 30: ...tDVH DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host tDVH tCYC tCYC tDVS tDVS tDH tDS tDH tDS t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD...

Page 31: ...DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tACK tACK tZAH tDVH tSS tLI Figure5 7 DeviceTerminatinganUltraDMADataInBurst tDVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0...

Page 32: ...5 0 at device tDVH tCYC tCYC tDVS tDVS tDS tDH t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDVS tDVH t...

Page 33: ...BE host DD 15 0 host tSR tRFS tRP Figure5 11 DevicePausinganUltraDMADataOutBurst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI t...

Page 34: ...TION 5 10 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tDVS tLI tLI tACK CRC tDVH tACK tIORDYZ tMLI tRP tRFS Figure5 13 DeviceTerminatinganU...

Page 35: ...egister A read only register containing specific information regarding the previous command Data interpretation differs depending on whether the controller is in operational or diagnostic mode A power...

Page 36: ...elect LBA Mode Enabling this bit for commands not supported by LBA mode will abort the selected command When set the Task File register contents are defined as follows for the Read Write and translate...

Page 37: ...ng retries disabled Write Verify Sector s 3Ch Write Sector Buffer E8h Write Multiple C5h Write DMA CAh CBh No retries ModeSet CheckCommands ModeSet CheckCommands ModeSet CheckCommands ModeSet CheckCom...

Page 38: ...F o r m at T ra ck 0 1 0 1 0 0 0 0 N N N Y Y S e e k 0 1 1 1 x x x x N N Y Y Y E xecu te D iag no sti c 1 0 0 1 0 0 0 0 N N N N D Initia li ze P a ra m e ter s 1 0 0 1 0 0 0 1 N Y N N Y R ea d S e cto...

Page 39: ...s the drive in the reset state Clearing the bit re enables the drive The software Reset bit must be held active for a minimum of 5 sec IRQ Enable Setting the Interrupt Request Enable to 0 enables the...

Page 40: ...The Busy bit does not clear until the reset clears and the drive completes initialization Completion of a reset operation does not generate a host interrupt Task File registers are initialized as fol...

Page 41: ...Commands WriteCommands WriteCommands Write Sector s Write Verify Sector s Write Sector Buffer Write DMA Multi word DMA Ultra DMA Write Multiple ModeSet CheckCommands ModeSet CheckCommands ModeSet Chec...

Page 42: ...egisters contain the numbers of the cylinder head and sector of the last sector read Back to back sector read commands set DRQ and generate an interrupt when the sector buffer is filled at the complet...

Page 43: ...cution is also similar to that of the READ SECTOR S command except that 1 Several sectors are transferred to the host as a block without intervening interrupts 2 DRQ qualification of the transfer is r...

Page 44: ...tor number of the last sector written The next time the buffer is ready to be filled during back to back Write Sector commands DRQ is set and an interrupt is generated After the host fills the buffer...

Page 45: ...Multiple commands report after the attempted disk write of the block or partial block in which the error occurred The write operation ends with the sector in error even if it was in the middle of a b...

Page 46: ...03h Set Transfer Mode based on value in Sector Count register 05h Enable Advanced Power Management 42h Enable Automatic Acoustic Management The sector count register contains the Automatic Ac oustic M...

Page 47: ...Lock Set Max Lock Set Max Lock Set Max Lock After this sub command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected The drive remains in this state un...

Page 48: ...he Automatic Power Down sequence Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Spin up and change time out value This command will spin up the spin motor if the drive is spun down I...

Page 49: ...the value placed in the Sector Count register is multiplied by five seconds to obtain the Time out Interval value If no drive commands are received from the host within the Time out Interval the drive...

Page 50: ...14 8 retired 7 1 removable media device 6 1 not removable controller and or device 5 3 retired 2 response incomplete 1 retired 0 reserved 1 Number of logical cylinders 2 Reserved 3 Number of logical...

Page 51: ...DMA transfer modes supported 64 15 8 reserved 7 0 advanced PIO transfer modes supported 65 Minimum multi word DMA transfer cycle time per word 15 0 cycle time in nanoseconds 66 Manufacturer s recommed...

Page 52: ...ted If words 82 and 83 0000h or FFFFh command set notification not supported 15 10 as c urrently defined 9 1 Automatic Acoustic Management feature set supported 8 0 as currently defined 88 Ultra DMA 1...

Page 53: ...the number of logical cylinders Upon receipt of the command the drive 1 Sets BSY 2 Saves the parameters 3 Resets BSY and 4 Generates an interrupt To specify maximum heads write 1 less than the maximum...

Page 54: ...is full the drive resets DRQ sets BSY and begins command execution If the drive is not already on the desired track an implied seek is performed Once at the desired track the data fields are written...

Page 55: ...codes are D0h S M A R T Read Attribute Value This feature returns 512 bytes of attribute information to the host D1h S M A R T Read Attribute Thresholds This feature returns 512 bytes of warranty fail...

Page 56: ...Maxtor s No Quibble Service policy By minimizing paperwork and processing No Quibble Service dramatically cuts the turnaround time normally required for repairs and returns Here s how it works 1 Custo...

Page 57: ...one phone to listen to technical information about Maxtor products and the top Q A s from our 24 hour automated voice system Continental USA 800 2MAXTOR 800 262 9867 Press 1 wait for announcement list...

Page 58: ...ess time The average time to make all possible length accesses seeks average seek time The average time to make all possible length seeks A typical measure of performance B B B B B bad block A block t...

Page 59: ...simultaneously under the set of read write heads This three dimensional storage volume can be accessed after a single seek cylinder zero The outermost cylinder in a drive that can be used for data st...

Page 60: ...ection code ECC A mathematical algorithm that can detect and correct errors in a data field This is accomplished with the aid of Check Bits added to the raw data error free A recording surface that ha...

Page 61: ...ference Used to update the physical disk address tracks and sectors of files and to expedite accesses inside diameter The smallest radial position used for the recording and playback of flux reversals...

Page 62: ...rocessor It is usually but not necessarily desktop size microprocessor A central processing unit CPU manufactured as a chip or a small number of chips missing pulse A term used in surface certificatio...

Page 63: ...re performed by the host processor using PIO register accesses to the data register plated thin film media Magnetic disk memory media having its surface plated with a thin coating of a metallic alloy...

Page 64: ...read write head on track can be either open loop quasi closed loop or closed loop servo track A track on a servo surface The prerecorded reference track on the dedicated servo surface of a disk drive...

Page 65: ...in question with or without repositioning the head V V V V V voice coil motor A positioning motor that uses the same principle as a voice coil in a loudspeaker The motor has no detent positions The me...

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