Maxtor 2R010H1, Specifications

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AT INTERFACE DESCRIPTION
5 – 4
DMA Timing DMA Timing DMA Timing DMA Timing DMA Timing
T IMIN G PARAMET ERS MODE 0 MODE 1 MODE 2
t0 Cycle Ti me ( min) 480 ns 150 ns 120 ns
tC DMAC K to DMARQ delay
tD DIOR-/D IOW- (min ) 215 ns 80 ns 70 ns
tE DIOR- data a cce ss (min) 150 ns 60 ns
tF DIOR- data hold (min ) 5 ns 5 ns 5 ns
tG DIOR-/DIOW- data setup ( min) 100 ns 30 ns 20 ns
tH DIOW- d ata hold ( min) 20 ns 15 ns 10 ns
tI DM AC K to DIOR-/D IOW - se tup (min) 0 0 0
tJ DIOR-/DIOW- to DMAC K ho ld ( min ) 20 ns 5 ns 5 ns
tKr DIOR- neg ated p uls e wi dth (min ) 50 ns 50 ns 25 ns
tKw D IOW - nega ted puls e wid th ( min ) 215 ns 50 ns 25 ns
tLr DIOR- to D MARQ delay (ma x) 120 ns 40 ns 35 ns
tL w DIOW- to D MARQ de la y (max) 40 ns 40 ns 35 ns
tZ DMAC K- to tr ista te (max) 20 ns 25 ns 25 ns
Figure 5 - 3
Multi-word DMA Data Transfer