Matrox Solios eV-CL, Installation And Hardware Reference

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Matrox Solios eV-CL acquisition section 49
Each interface is controlled by a universal asynchronous receiver-transmitter
(UART)
*
. Each UART features independently programmable baud rates,
supporting all standard baud rates from 300 baud up to 230400
†
baud.
PSGs
Matrox Solios eV-CLB and eV-CLBL in dual-Base configuration feature two
programmable synchronization generators (PSGs). Matrox Solios eV-CLB and
eV-CLBL, in single-Medium configuration, and Matrox Solios eV-CLF and
eV-CLFL feature one PSG. Each PSG allows for independent acquisition from
one video source, since they are responsible for managing all video timing and
synchronization signals.
The PSGs are also responsible for managing the camera control and auxiliary
signals supported by the board. These signals are configurable signals that can
support one or several functions, one of which is user-defined; the table in the
next subsection identifies the functions to which the camera control and auxiliary
signals can be defined. The PSGs are also responsible for implementing the
functionality to which these can be defined.
Camera control and auxiliary signals
The following table summarizes the auxiliary functionality that the PSGs support,
and the corresponding signals that the PSGs can receive/generate on Matrox Solios
eV-CLB and Matrox Solios eV-CLF. For example, P0_TTL_AUX_IO_0 can be
defined as a timer output (M_TIMER3), trigger input (trigger controller 0 on acq
path 0), field polarity input, user input, or user output (M_USER_BIT2) signal.
Note that all auxiliary input signals are inquirable so they can be used for user
input, although not listed in the following table as a possible functionality.
*. The UART implementation was derived from a design by Daniel Wallner. Please see
Appendix C: Acknowledgments for copyright information.
†. The maximum baud rate is highly dependent on the amount of computer resources
available.