Marantz SR4500, Service Manual

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43 44
IC81 : NJU3430FG1
66 P60/_DREQ0 I/O NJW1157DATA - O - L NJW1157/CS42418 Data Input
67 VSS I VSS - - - GND
68 VSS I VSS - - - GND
69 P61/_TEND0 I/O NJW1157CLK
-
O
-
L NJW1157/CS42418 Clock Input
70 P62/_DREQ1 I/O NJW1157LATCH - O
-
L NJW1157 Latch Input
71 P63/_TEND1 I/O N.C.
-
O L L Open
72
P27/PO7/TIOCB5/
TMO1
I/O FLRA_ON - O H L Front Speaker On/Off
73
P26/PO6/TIOCA5/
TMO0
I/O N.C. - O - L Open
74
P25/PO5/TIOCB4/
TMCI1
I/O SURR_ON - O H L SURR/CNT Speaker On/Off
75
P24/PO4/TIOCA4/
TMRI1
I/O AVSS - O H L Power Amp
±
B_L_Sel
76
P23/PO3/TIOCD3/
TMCI0
I/O _HEAT_DET - I H -
Power Amp Heat sink
TempDetect
77
P22/PO2/TIOCC3/
TMRI0
I/O _STANDBY - O L L Standby Power
78 P21/PO1/TIOCB3 I/O _HP_DET - I L - HP Jack Detect
79 P20/PO0/TIOCA3 I/O HP_ON - O H L Head Phone On
80 VCL I VCL - - - -
81 _RES I _RST - L - Reset
82 NMI I NMI - - - Fix H(At the time of the un-use)
83 _STBY I _STBY - L H FixH
84 VCC I Vcc - - - +5V
85 XTAL I XTAL - - - Xtal(20M)
86 EXTAL I EXTAL - - - Xtal(20M)
87 VSS I VSS -
-
-
-
-
-
-
-
- - GND
88 PF7/<B I/O SEL- - I - - Front Select. Encoder
89 VCC I Vcc - - - - +5V
90 PF6 I/O SEL+ - I - Front Select. Encoder
91 PF5 I/O _STBY LED L O L H Standby LED On
92 PF4 I/O _RSFL
-
O L L Front FL Driver
93 PF3 I/O VOL-
-
I
-
Front Vol. Encoder
94 PF2 I/O VOL+
-
I
-
Front Vol. Encoder
95 PF1 I/O CTS - I -
-
-
-
- UART
96 PF0 I/O RTS H O H - UART
97 P50/TxD2/_IRQ4 I/O OSDDATA - O - L NJU3430 Data Input
98 P51/RxD2/_IRQ5 I N.C - I - - Pull Down 10k
99 VSS I VSS - - - GND
100 VSS I VSS -
-
-
- - GND
101 P52/SCK2/_IRQ6 I/O OSDCLK - O - L NJU3430 Clock Input
102
P53/_ADTRG/
_IRQ7
I/O _RSTFL - O L L Reset FL Driver
103 AVCC I AVCC - - - +5V
104 Vref I VREF -
-
-
- - +5V
105 P40/AN0 I KEY0 - AD - Front Key
106 P41/AN1 I KEYBÒ - AD - Front Key
107 P42/AN2 I KEY2 - AD - Front Key
108 P43/AN3 I N.C. - I - Pull Up 47k
109 P44/AN4 I P_LINE_FAIL - AD - Emergency Protection
110 P45/AN5 I MODE - AD - CPU mode
111 P46/AN6/DA0 I N.C. - I - Open
112 P47/AN7/DA1 I N.C. - AD -
-
-
-
-
-
-
-
- Pull Down 47k
113 AVSS I VSS - - - - GND
65 VSS I VSS -
-
-
- - - GND
114 VSS I VSS - - - - GND
115
P17/PO15/TIOCB2/
TCLKD
I/O SB_ON - O H L Surroud Back On: H / Off: L
116
P16/PO14/
TIOCA2
I/O RC_OUT - O - L RC BUS Output
117
P15/PO13/TIOCB1/
TCLKC
I/O N.C. - O - - Pull Up 47k
118
P14/PO12/
TIOCA1
I/O N.C. - O - L Open
119
P13/PO11/TIOCD0/
TCLKB
I/O KILLIR L O H L Kill to IR input signal.
120
P12/PO10/TIOCC0/
TCLKA
I/O N.C. - O - L Open
121
P11/PO9/TIOCB0/
_DACK1
I/O N.C. - O - L Open
122
P10/PO8/TIOCA0/
_DACK0
I/O RC_IN - T_IN
↑↓
- IR In for RC-5
123 MD0 I MD0 - YES - +5VL
124 MD1 I MD1 - YES - Fix H
125 MD2 I MD2 - YES -
-
-
- Normal :H, Boot :L
126 PG0 I/O _FCS - O L H DSP Chip Enable
127 PG1 I/O _RSTDSP
-
O L L DSP Reset
128 PG2 I/O _SCS
-
O L H DSP Chip Enable
pin port I/O Name STBY Note
mode = 7 set use Act. init
Port Setting
SI
CS
C L K
R S
V
S S
OSC
1
OSC
2
V
D D
R S T
V
F DP
M K
1
~ M K
2
S
1
~
S
35
P
1
T
1
~
T
1 6
8bits
Shift
R e g .
Instruction
D ec oder
Timing
Gen.
C R
OSC .
State
Reg.
Display
Control
Address
Selector
Read
Address
Counter
L i n e
Address
Counter
Timing
D r i v e r
D D R A M
1 6 x 8 bit
C G R O M
8 , 4 0 0 b i t
Port
D r i v e r
C G R A M
3 5 x 8 bit
Segment
D r i v e r
M K R A M
1 6 x 2 bit
Icon
D r i v e r
R ESET
N o . S Y M B O L I/O F U N C T I O N
5 7 V
D D
- P o w e r S o u r c e : V
D D
= + 3 . 0 t o 5 . 5 V
4 9 V
S S
- G N D : V
S S
= 0 V
4 8 V
F D P
-
V F D D r i v i n g P o w e r S o u r s e
V
D D
- 2 0 V t o V
D D
- 4 5 V
5 0 O S C
1
I
C R O s c i l l a t i o n T e r m i n a l
E x t e r n a l R a n d C c o n n e c t t o t h e s e t e r m i n a l s .
(Target f
O S C
= 3 6 0 k H z )
5 1 O S C
2
O
5 4 C L K I
S e r i a l C l o c k I n p u t T e r m i n a l
T h e s e r i a l d a t a i n p u t s y n c h r o n i z i n g t h e r i s e e d g e o f t h i s
terminal.
5 3 C S I
C h i p S e l e c t T e r m i n a l
W h e n t h e C S t e r m i n a l i s " H " t h e s e r i a l d a t a i n p u t i s n o t
a v a i l a b l e .
5 5 S I I
S e r i a l D a t a I n p u t T e r m i n a l
T h e d a t a i n p u t i s M S B f i r s t .
5 6 R S I
R e g i s t e r S e l e c t i o n S i g n a l I n p u t T e r m i n a l
R S = " 0 " : I n s t r u c t i o n R e g i s t e r
R S = " 1 " : D a t a R e g i s t e r
5 2 R S T I
R e s e t T e r m i n a l R S T = " L " : R e s e t
- E a c h A d d r e s s
- E a c h R A M D a t a
- D i s p l a y D i g i t s
- C o n t r a s t C o n t r o l
-All Display Off
- A l l O u t p u t s a r e " L " : ( 0 0 )
H
: Unfixed
: 1 6 - d i g i t
: 8/16 Dury
6 1 t o 6 4 ,
1 t o 3 1
S
1
to S
3 5
O
Segment Output Terminals (Internal Pull-down
R e s i s t a n c e )
3 2 t o 4 7 T
1
to T
1 6
O Timing Output Terminals (Internal Pull-down Resistance)
6 0
5 9 M K
1
M K
2
O Icon Output Terminals (Internal Pull-down Resistance)
5 8 P
1
O
O u t p u t P o r t T e r m i n a l
T h i s t e r m i n a l i s s u i t a b l e f o r L E D .
IC41 : H8S2398