MLC3730
127
‐
D16
128
‐
C16
129
‐
C17
130
‐
B17
131
‐
E13
132
‐
D14
133
‐
A17
134
‐
A16
135
‐
B16
136
‐
B15
137
‐
A15
138
‐
A14
139
‐
B14
140
‐
B13
141
‐
A13
142
‐
E9
143
‐
D10
144
‐
D13
145
‐
D9
146
‐
D12
147
‐
D8
148
‐
E11
149
‐
D7
150
‐
D11
151
‐
E7
152
‐
D6
153
‐
A12
154
‐
B12
155
‐
B11
156
‐
A11
157
‐
B10
158
‐
A10
159
‐
B9
160
‐
A9
161
‐
B8
162
‐
A8
163
‐
A7
164
‐
B7
165
‐
D5
166
‐
B6
167
‐
A6
168
‐
A5
169
‐
B5
170
‐
B4
171
‐
A4
172
‐
A3
173
‐
B3
174
‐
B2
0x
PD[11]
PD[12]
PD[13]
PD[14]
VSS33IO
VDD33IO
PD[15]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD12INT
PNTRST
PGPD00
PTDI
PGPD01
PTMS
PGPD02
PTCK
PGPD03
PTDO
PRTCK
PGPA00
PGPA01
PGPA02
PGPA03
VSS33IO
VDD33IO
VSS12INT
VDD12INT
VSS33USB11
PUDP11
PUDN11
VDD33USB1
PAIN[4]
PAIN[3]
PAIN[2]
PAIN[1]
PAIN[0]
VSS33ADC
VDD33ADC
PGPA04
PGPA05
PGPA06
B
B
B
B
GND
POWER
B
B
B
B
B
B
B
B
B
POWER
ISPU
BS
ISPU
BS
ISPU
BS
ISPU
BS
B
O
BS
BS
BS
BS
GND
POWER
GND
POWER
1
GND
B
B
1
POWER
AI
AI
AI
AI
AI
AGND
APOWER
BS
BS
BS
Externa
Externa
Externa
Externa
VSS
3.3
VDD
3.3
Externa
Externa
Externa
Externa
Externa
Externa
Externa
Externa
Externa
VDD
1.2
ARM92
ARM92
ARM92
ARM92
ARM92
ARM92
SPI0
‐
MC
SPI0
‐
M
SPI0
‐
M
SPI0
‐
MC
VSS
3.3
VDD
3.3
VSS
1.2
VDD
1.2
USB
1.1
USB1.1
USB1.1
USB
1.1
ADC
an
ADC
an
ADC
an
ADC
an
ADC
an
ADC
Gr
R
ADC
3.3
SPI0
‐
MC
SPI0
‐
MC
SPI0
‐
MC
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
V
Digital
I/O
G
3V
Digital
I/O
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
al
Bank, SDRA
2V
Digital
Inte
26ejs
JTAG
tes
SDIO1
‐
D
SDIO1
‐
D
26ejs
JTAG
tes
26ejs
JTAG
tes
26ejs
JTAG
tes
SDIO1
‐
D
SDIO1
‐
C
26ejs
JTAG
tes
26ejs
JTAG
tes
CK
DI/SDO
DO
CS0
V
Digital
I/O
G
3V
Digital
I/O
V
Digital
Inter
2V
Digital
Inte
1:
Transceiver
DP
bi
‐
directio
DN
bi
‐
directi
1:
Transceiver
alog
input
[4]
alog
input
[3]
alog
input
[2]
alog
input
[1]
alog
input
[0]
ound
3V
Power
CS1
CS2
HU3
‐
CS3
HU3
‐
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
Ground
Power
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
M,
NAND
Flas
ernal
Core
Pow
t
reset
input
D5/
DxOE
HU
t
data
input
HU
t
mode
select
HU
t
clock
input
D6/
MDOE
NA
t
data
output
t
clock
output
Ground
Power
rnal
Core
Gro
ernal
Core
Pow
Ground
onal
I/O
PAD
(
onal
I/O
PAD
Power
‐
TXD
TOU
‐
RXD
TOU
sh
data
bus
[1
sh
data
bus
[1
sh
data
bus
[1
sh
data
bus
[1
sh
data
bus
[1
sh
data
bus
[0
sh
data
bus
[1
sh
data
bus
[2
sh
data
bus
[3
sh
data
bus
[4
sh
data
bus
[5
sh
data
bus
[6
sh
data
bus
[7
wer
5
‐
RXD
5
‐
CTS
T
tion
input
5
‐
RDY
T
ND
‐
CEB1
H
(Tri
‐
state
out
t
und
wer
(3.3V
interfac
(3.3V
interfac
UT2
SDIO
SDIO
UT3
SDIO
SDIO
11]
input/outp
12]
input/outp
13]
input/outp
14]
input/outp
15]
input/outp
0]
input/outpu
1]
input/outpu
2]
input/outpu
3]
input/outpu
4]
input/outpu
5]
input/outpu
6]
input/outpu
7]
input/outpu
TOUT2
TOUT3
S
S
HU5
‐
CTS
tput)
ce)
ce)
O1
‐
D5/
O1
‐
DxOE
O1
‐
D6/
O1
‐
CMDOE
24/305
put
put
put
put
put
ut
ut
ut
ut
ut
ut
ut
ut
SDIO2
‐
D7/
SDIO2
‐
18POW
DRVVBUS20
PAD21
PAD22
5
W
MLC3730
175
‐
A2
176
‐
A1
1.3.3
Device
MLC3730S
MLC3730SD
MLC3730ST
0x
PGPA07
PGPA08
[Table
1]
D
OLBY
&
D
Fu
no
Do
Do
BS
BS
]
MLC37
TS
S
UPPORTI
unction
ormal
olby
olby/DTS
I2C0
‐
SC
I2C0
‐
SD
30S
X
,
MLC373
ING
D
EVICE
0x800
DEVID
“00”
“01”
“10”
CL
DA
30M6,
MLC37
00_0004
regis
D[9:8]
30M1
176
‐
BG
ster
GA
P
IN
D
ESCRIPTTIONS
25/305
5
70