MagnaChip MC80F0104, User Manual, Page: 93 / 126

Preliminary MC80F0104/0204
Mar. 2005 Ver 0.2 89
.
Figure 19-2 SLEEP Mode Release Timing by External Interrupt
Figure 19-3 Timing of SLEEP Mode Release by Reset
19.2 Stop Mode
In the Stop mode, the main oscillator, system clock and pe-
ripheral clock is stopped, but RC-oscillated watchdog tim-
er continue to operate. With the clock frozen, all functions
are stopped, but the on-chip RAM and Control registers are
held. The port pins out the values held by their respective
port data register, port direction registers. Oscillator stops
and the systems internal operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
"STOP" which starts the STOP operating mode.
Note:
The Stop mode is activated by execution of STOP instruc-
tion after setting the SSCR to “5A
H
”. (This register should be writ-
ten by byte operation. If this register is set by bit manipulation
instruction, for example "set1" or "clr1" instruction, it may be undes-
ired operation)
In the Stop mode of operation, V
DD
can be reduced to min-
imize power consumption. Care must be taken, however,
to ensure that V
DD
is not reduced before the Stop mode is
invoked, and that V
DD
is restored to its normal operating
level, before the Stop mode is terminated.
Oscillator
(X
IN
pin)
~~
Normal Operation SLEEP Operation
~~
~~
~~
~~
External Interrupt
Internal Clock
SLEEP Instruction
Executed
~~
Normal Operation
~~
~~
~~
SLEEP Instruction
Stabilization Time
t
ST
= 65.5mS @4MHz
Internal
~~
~~
~~
RESET
RESET
Oscillator
(X
IN
pin)
~~
CPU
Clock
~~
~~
Execution
Normal Operation SLEEP Operation Normal Operation