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MC80F0104/0204

Preliminary

28

 

 

Mar. 2005 Ver 0.2

0ECH

IRQH

INT0IF

INT1IF

INT2IF

INT3IF

RXIF

TXIF

SIOIF

T0IF

0EDH

IRQL

T1IF

T2IF

T3IF

T4IF

ADCIF

WDTIF

WTIF

BITIF

0EEH

IEDS

IED3H

IED3L

IED2H

IED2L

IED1H

IED1L

IED0H

IED0L

0EFH

ADCM

ADEN

ADCK

ADS3

ADS2

ADS1

ADS0

ADST

ADSF

0F0H

ADCRH

PSSEL1

PSSEL0

ADC8

-

-

-

ADC Result Reg. High

0F1H

ADCRL

ADC Result Register Low

0F2H

BITR

1

Basic Interval Timer Data Register

CKCTLR

1

ADRST

-

RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

0F4H

WDTR

WDTCL

7-bit Watchdog Timer Register

WDTDR

Watchdog Timer Data Register (Counter Register)

0F5H

SSCR

Stop & Sleep Mode Control Register

0F7H

PFDR

-

-

-

-

-

PFDEN

PFDM

PFDS

0F8H

PSR0

PWM3O

PWM1O

EC1E

EC0E

INT3E

INT2E

INT1E

INT0E

0F9H

PSR1

-

-

-

-

AVREFS

BUZO

T2O

T0O

0FCH

PU0

R0 Pull-up Selection Register

0FDH

PU1

R1 Pull-up Selection Register

0FFH

PU3

R3 Pull-up Selection Register

1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.

Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be 

accessed by register operation instruction such as "LDM dp,#imm".

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Table 8-2 Control Register Function Description

Summary of Contents for MC80F0104

Page 1: ...MAGNACHIP SEMICONDUCTOR LTD 8 BIT SINGLE CHIP MICROCONTROLLERS MC80F0104 0204 MC80C0104 0204 Preliminary User s Manual Ver 0 2...

Page 2: ...onductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however MagnaChip semi...

Page 3: ...ATION 18 Registers 18 Program Memory 21 Data Memory 24 Addressing Mode 29 9 I O PORTS 33 R0 and R0IO register 33 R1 and R1IO register 34 R3 and R3IO register 36 10 CLOCK GENERATOR 37 Oscillation Circu...

Page 4: ...ER FAIL PROCESSOR 98 22 COUNTERMEASURE OF NOISE 100 Oscillation Noise Protector 100 Oscillation Fail Processor 101 23 Device Configuration Area 102 24 MASK Option MC80C0104 0204 103 25 Emulator EVA Bo...

Page 5: ...functions are same as below table 1 2 Features 4K Bytes On chip FLASH Endurance 100 times Retention time 10 years 256 Bytes On chip Data RAM Included stack memory Minimum Instruction Execution Time 33...

Page 6: ...ured macro as sembler an in circuit emulator CHOICE Dr TM and OTP pro grammers There are two different type of programmers such as single type and gang type For mode detail Macro assembler op erates u...

Page 7: ...size Package Mask version MC80C0204B MC80C0204D MC80C0104B MC80C0104D 4K bytes 4K bytes 4K bytes 4K bytes 256 bytes 20PDIP 20SOP 16PDIP 16SOP FLASH version MC80F0204B MC80F0204D MC80F0104B MC80F0104D...

Page 8: ...Timer Interval Watch dog Timer Instruction R0 R1 Buzzer Driver PSW System controller Timing generator System Clock Controller Clock Generator RESET R00 INT3 SCK R01 AN1 SI R02 AN2 SOUT R03 AN3 INT2 R0...

Page 9: ...0 PDIP 19 18 17 16 15 14 13 12 11 16 PDIP R12 INT1 BUZO R13 R14 MC80F0204B 0204D MC80F0104B 0104D R03 AN3 INT2 R04 AN4 EC0 RXD 20 16 SOP 2 3 4 5 6 7 8 9 10 1 MC80F0204B 0204D R02 AN2 SOUT R01 AN1 SI R...

Page 10: ...1 043 0 050 TYP 0 100 TYP 0 300 0 270 0 014 0 15 MAX 0 180 MIN 0 015 0 120 20 PDIP unit inch MAX MIN 1 010 0 021 0 140 0 065 0 008 0 245 0 015 0 291 0 398 0 5118 0 104 0 013 TYP 0 050 0 004 0 0091 0 8...

Page 11: ...050 TYP 0 100 TYP 0 300 0 260 0 014 0 15 MAX 0 180 MIN 0 015 0 120 0 292 0 398 0 412 0 104 0 014 TYP 0 050 0 004 0 0091 0 8 0 016 16 PDIP 16 SOP unit inch MAX MIN 0 745 0 022 0 140 0 065 0 008 0 240 0...

Page 12: ...3IO R3 serves the functions of the serial interface following special features in Table 5 3 Port pin Alternate function R00 R01 R02 R03 R04 R05 R06 R07 INT3 External Interrupt Input Port3 SCK SPI CLK...

Page 13: ...Port 3 External Interrupt Input2 R04 AN4 EC0 RXD 1 I O Input Input Input Analog Input Port 4 Event Counter Input 0 UART Data Input R05 AN5 T0O TXD 2 I O Input Output Output Analog Input Port 5 Timer0...

Page 14: ...ADEN ADS 3 0 ADCM VDD VSS Pin Data Reg Direction Reg Pull up Tr Pull up Reg MUX VDD Data Bus VDD VSS Open Drain Reg SI SI_EN SIOM Noise Filter RD AN 1 ADEN ADS 3 0 VDD VSS Pin Data Reg Direction Reg P...

Page 15: ...Filter RD VDD VSS Pin Data Reg Direction Reg Pull up Tr Pull up Reg MUX VDD Data Bus VDD VSS Open Drain Reg INT1E PSR0 1 MUX PWM3OE PSR0 7 BUZOE PSR1 2 PWM3O BUZO SOUT SI SO_OUT_EN SIOM Noise Filter R...

Page 16: ...ADCM AN 0 ADEN ADS 3 0 RD VDD VSS Pin Data Reg Direction Reg Pull up Tr Pull up Reg MUX VDD Data Bus VDD VSS Open Drain Reg MUX PWM1OE PSR0 6 PWM1O ADC Reference AVREFS PSR1 3 ADCM MUX VDD Voltage Inp...

Page 17: ...IN CLOCK fXIN 4 RD VDD VSS Data Reg Direction Reg Pull up Tr Pull up Reg MUX VDD Data Bus VDD VSS Open Drain Reg RD VDD VSS XOUT Data Reg Direction Reg Pull up Tr Pull up Reg MUX VDD Data Bus VDD VSS...

Page 18: ...for extended periods may affect device reliability 7 2 Recommended Operating Conditions 7 3 A D Converter Characteristics Ta 40 85 C VSS 0V VDD 2 7 5 5V fXIN 8MHz Parameter Symbol Condition Min Max U...

Page 19: ...L2 XIN VDD 5V 15 A Hysteresis VT Hysteresis Input1 VDD 5V 0 5 V PFD Voltage VPFD VDD 2 0 3 0 V POR Voltage VPOR VDD 2 4 V POR Start Voltage2 VSTART VDD 0 TBD V POR Rising Time2 TRISE VDD TBD V ms Inte...

Page 20: ...requency fCP XIN 1 8 MHz External Clock Pulse Width tCPW XIN 50 nS External Clock Transition Time tRCP tFCP XIN 20 nS Oscillation Stabilizing Time tST XIN XOUT 20 mS External Input Pulse Width tEPW IN...

Page 21: ...side specified operating range e g outside specified VDD range This is for information only and devices are guaranteed to operate properly only within the specified range The data presented in this se...

Page 22: ...is accepted However if it is used in excess of the stack area permitted by the data memory allocating configuration the user processed data may be lost The stack can be located at any position within...

Page 23: ...t addressing mode addressing area is from zero page 00H to 0FFH when this flag is 0 If it is set to 1 addressing area is assigned 100H to 1FFH It is set by SETG instruction and cleared by CLRG Overflo...

Page 24: ...01FC 01FD 01FE 01FF 01FF Push down PSW At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FD Pop up At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FC Pop up PSW 01...

Page 25: ...own in Figure 8 7 Example Usage of TCALL The interrupt causes the CPU to jump to specific location where it commences the execution of the service routine The External interrupt 0 for example is assig...

Page 26: ...Area 256 Bytes means that the BRK software interrupt is using same address with TCALL0 NOTE TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL...

Page 27: ...x DW RX UART Rx DW INT3 Ext Int 3 DW INT2 Ext Int 2 DW INT1 Ext Int 1 DW INT0 Ext Int 0 DW RESET Reset ORG 0F000H 4K bytes ROM Start address MAIN PROGRAM RESET DI Disable All Interrupt RAM Clear Routi...

Page 28: ...be accessed by bit manipula tion instruction Do not use read modify write instruction Use byte manipulation instruction for example LDM Example To write at CKCTLR LDM CKCTLR 0AH Divide ratio 32 Stack...

Page 29: ...0 0 0 0 0 00D2 Timer 1 mode control register TM1 R W 0 0 0 0 0 0 0 0 byte bit 00D3 Timer 1 data register TDR1 W 1 1 1 1 1 1 1 1 byte Timer 1 PWM period register T1PPR W 1 1 1 1 1 1 1 1 byte 00D4 Timer...

Page 30: ...t low register ADCRL R Undefined byte 00F2 Basic interval timer register BITR R Undefined byte Clock control register CKCTLR W 0 0 1 0 1 1 1 00F4 Watch dog timer register WDTR W 0 1 1 1 1 1 1 1 byte W...

Page 31: ...Timer1 Capture Data Register 0D5H PWM1HR Timer1 PWM High Register 0D6H TM2 CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST 0D7H T2 TDR2 CDR2 Timer2 Register Timer2 Data Register Timer2 Capture Data Register 0D8H TM3...

Page 32: ...er Data Register Counter Register 0F5H SSCR Stop Sleep Mode Control Register 0F7H PFDR PFDEN PFDM PFDS 0F8H PSR0 PWM3O PWM1O EC1E EC0E INT3E INT2E INT1E INT0E 0F9H PSR1 AVREFS BUZO T2O T0O 0FCH PU0 R0...

Page 33: ...55H 8 4 3 Direct Page Addressing dp In this mode a address is specified within direct page Example G 0 C535 LDA 35H A RAM 35H 8 4 4 Absolute Addressing abs Absolute addressing sets corresponding memo...

Page 34: ...of com mand plus the data of X register And it assigns the mem ory in Direct page ADC AND CMP EOR LDA LDY OR SBC STA STY XMA ASL DEC INC LSR ROL ROR Example G 0 X 0F5H C645 LDA 45H X Y indexed direct...

Page 35: ...ct page ADC AND CMP EOR LDA OR SBC STA Example G 0 X 10H 1625 ADC 25H X Y indexed indirect dp Y Processes memory data as Data assigned by the data dp 1 dp of 16 bit pair memory paired by Operand in Di...

Page 36: ...MC80F0104 0204 Preliminary 32 Mar 2005 Ver 0 2 1F25E0 JMP 0C025H 25 0E025H jump to E0 0FA00H E7 0E026H 25 0E725H NEXT 1F PROGRAM MEMORY address 0E30AH...

Page 37: ...gh R07 pins are used as input ports an on chip pull up resistor can be connected to them in 1 bit units with a pull up selection register 0 PU0 Each I O pin of R0 port can be used to open drain output...

Page 38: ...can be used to open drain output port by setting the corre sponding bit of the open drain selection register 1 R1OD In addition Port R1 is multiplexed with various alternate functions The port selecti...

Page 39: ...ion R1 Open Drain R1OD ADDRESS 0C9H RESET VALUE 0 0000B Selection Register 0 Disable 1 Enable Open Drain Resister Selection PSR0 ADDRESS 0F8H RESET VALUE 0000 0000B INT2E Port INT Selection 0 R11 R12...

Page 40: ...ons R31 and R32 can be used as ADC input channel 14 and 15 by setting ADCM to enable ADC and select chan nel 14 and 15 R33 R34 and R35 is multiplexed with XIN XOUT and RESET pin These pins can be used...

Page 41: ...igure 10 1 Block Diagram of Clock Generator 10 1 Oscillation Circuit XIN and XOUT are the input and output respectively a in verting amplifier which can be set for use as an on chip os cillator as sho...

Page 42: ...REXT and capacitor CEXT values and the operating temperature The user needs to take into account variation due to toler ance of external R and C components used Figure 10 5 shows how the RC combinatio...

Page 43: ...r one machine cycle by hardware If the STOP instruction executed after writing 1 to bit RCWDT of CKCTLR it goes into the internal RC oscillat ed watchdog timer mode In this mode all of the block is ha...

Page 44: ...rce clock select 000 fXIN 8 001 fXIN 16 010 fXIN 32 011 fXIN 64 100 fXIN 128 101 fXIN 256 110 fXIN 512 111 fXIN 1024 Clear bit 0 Normal operation free run 1 Clear 8 bit counter BITR to 0 This bit beco...

Page 45: ...with the bit WDTON Note Because the watchdog timer counter is enabled after clear ing Basic Interval Timer after the bit WDTON set to 1 maximum error of timer is depend on prescaler ratio of Basic In...

Page 46: ...CKCTLR to 1 WDTON is initialized to 0 during re set and it should be set to 1 to operate after reset is re leased Example Enables watchdog timer for Reset LDM CKCTLR xxx1_xxxxB WDTON 1 The watchdog t...

Page 47: ...is gen erated which drives the RESET pin low to reset the inter nal hardware The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode 2 3 n Source clock Bina...

Page 48: ...t has six operating modes 8 bit timer counter 16 bit timer counter 8 bit capture 16 bit capture 8 bit compare output and 10 bit PWM which are selected by bit in Timer mode register TM0 and TM1 as show...

Page 49: ...TCL 5 4 3 2 1 0 T0CN INITIAL VALUE 00 0000B ADDRESS 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 Bit Name Bit Position Description CAP0 TM0 5 0 Timer Counter mode 1 Capture mode selection flag T0CK2 T0CK1 T0C...

Page 50: ...BTCL 5 4 3 2 1 0 T2CN INITIAL VALUE 00 0000B ADDRESS 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 Bit Name Bit Position Description CAP2 TM2 5 0 Timer Counter mode 1 Capture mode selection flag T2CK2 T2CK1 T2...

Page 51: ...rnal clock input The inter nal clock has a prescaler divide ratio option of 1 2 4 8 16 32 64 128 256 512 1024 2048 or external clock select ed by control bits TxCK0 TxCK1 TxCK2 of register TMx Figure...

Page 52: ...TIMER 3 INTERRUPT 1 4 16 TDR2 8 bit TDR3 8 bit T3 8 bit T2 8 bit Comparator Comparator TIMER 2 TIMER 3 BTCL 7 6 5 4 3 2 1 0 T2CN INITIAL VALUE 000000B ADDRESS 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 X X...

Page 53: ...ter TM2 or 1 4 16 selected by control bits T3CK 1 0 of reg ister TM3 In the Timer 0 timer register T0 increases from 00H until it matches TDR0 and then reset to 00H The match output of Timer 0 generat...

Page 54: ...to use event counter function the bit 4 5 of the Port Selection Register PSR0 address 0F8H is required to be set to 1 After reset the value of timer data register TDRn is initial ized to 0 The interva...

Page 55: ...Ver 0 2 51 Figure 13 8 Count Operation of Timer Event counter Timer 1 T1IF Interrupt TDR1 TIME Occur interrupt Occur interrupt stop clear start disable enable Start Stop T1ST T1CN Control count u p c...

Page 56: ...16BIT of TM3 should be set to 1 respec tively as shown in Figure 13 10 Even if the Timer 0 including Timer 1 is used as a 16 bit timer the Timer 2 and Timer 3 can still be used as either two 8 bit tim...

Page 57: ...t CAP0 of timer mode register TM0 bit CAP1 of timer mode register TM1 for Timer 1 as shown in Figure 13 11 Likewise the Tim er 2 capture mode is set by bit CAP2 of timer mode register TM2 bit CAP3 of...

Page 58: ...s more little than wanted value It can be ob tained correct value by counting the number of timer over flow occurrence Timer Counter still does the above but with the added fea ture that a edge transi...

Page 59: ...CK 1 0 11 00 01 1 2 8 32 128 512 2048 011 100 101 110 10 INT0 PIN INT1IF 0 Stop 1 Clear and start T1ST INT1 INTERRUPT T1CN CDR1 8 bit T1 8 bit 01 10 11 Capture IEDS 3 2 INT1 PIN BTCL 7 6 5 4 3 2 1 0 T...

Page 60: ...CK 1 0 11 00 01 1 4 16 16 64 256 1024 011 100 101 110 10 INT2 PIN INT3IF 0 Stop 1 Clear and start T3ST INT3 INTERRUPT T3CN CDR3 8 bit T3 8 bit 01 10 11 Capture IEDS 7 6 INT3 PIN BTCL 7 6 5 4 3 2 1 0 T...

Page 61: ...t INT0 Pin Interrupt Request T0 TIME u p c o u n t 0 1 2 3 4 5 6 7 8 9 n n 1 Capture Timer Stop Clear Start Interrupt Interval Period Delay INT0IF Ext INT0 Pin Interrupt Request INT0IF This value is l...

Page 62: ...bit mode the bits T3CK1 T3CK0 CAP3 and 16BIT of TM3 should be set to 1 respectively as shown in Figure 13 16 Figure 13 15 16 bit Capture Mode of Timer 0 1 0 Stop 1 Clear and start T0ST T0CN Capture CD...

Page 63: ..._0001B INT0 set LDM TM0 0010_1111B CaptureMode LDM TM1 0100_1100B 16bit Mode LDM TDR0 0FFH LDM TDR1 0FFH LDM IEDS 01H Falling Edge SET1 T0E EI 0 Stop 1 Clear and start T2ST T2CN Capture CDR3 CDR2 High...

Page 64: ...1 3 Duty PWM3HR 1 0 T3PDR X Source Clock The relation of frequency and resolution is in inverse pro portion Table 13 3 shows the relation of PWM frequency vs resolution If it needed more higher freque...

Page 65: ...B ADDRESS 0D5H T1PWHR X The value 0 or 1 corresponding your operation BTCL 7 6 5 4 3 2 1 0 T3PWHR1 T3PWHR0 T3PWHR2 T3PWHR3 X X X X W W W W INITIAL VALUE 0FFH ADDRESS 0D3H T1PPR BTCL 7 6 5 4 3 2 1 0 W...

Page 66: ...ADDRESS 0DBH T3PWHR X The value 0 or 1 corresponding your operation BTCL 7 6 5 4 3 2 1 0 T3PWHR1 T3PWHR0 T3PWHR2 T3PWHR3 X X X X W W W W INITIAL VALUE 0FFH ADDRESS 0D9H T3PPR BTCL 7 6 5 4 3 2 1 0 W W...

Page 67: ...HR 0CH T1PPR FFH T1PDR 7FH T1CK 1 0 00 XIN T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0 T1PPR 8 bit T1PDR 8 bit Period Duty 1 1 FFH 0 0 7FH 00 clock PWM1E T1ST T1CN 00 3FF Source T1 PWM1O POL 1 Duty Cycle Period C...

Page 68: ...RH and ADCRL contains the re sults of the A D conversion When the conversion is completed the result is loaded into the ADCRH and AD CRL the A D conversion status bit ADSF is set to 1 and the A D inte...

Page 69: ...adjacent to the pin undergoing A D conversion 4 AVDD pin input impedance A series resistor string of approximately 5K is connected between the AVREF pin and the VSS pin Therefore if the output impedan...

Page 70: ...cycle bit is cleared to 0 by hardware ADS1 ADS0 ADS3 ADS2 ADCK 1110 Channel 14 AN14 A D converter Enable bit 0 A D converter module turn off and current is not flow 1 Enable A D converter INITIAL VALU...

Page 71: ...it as illustrated in Figure 15 1 The SO pin is designed to input and output So the Serial I O SIO can be operated with minimum two pin Pin R00 SCK R01 SI and R02 SO pins are controlled by the Serial M...

Page 72: ...red BTCL 7 6 5 4 3 2 1 0 IOSW POL SIOST Serial transmission status bit Serial transmission Clock selection INITIAL VALUE 0000 0001B ADDRESS 0E2H SIOM SIOSF Serial Input Pin Selection bit 0 SI Pin Sele...

Page 73: ...OL 1 D1 D2 D3 D4 D6 D7 D0 D5 D1 D2 D3 D4 D6 D7 D0 D5 SIOST SCK R42 POL 0 SO P44 SI R43 SIOIF SIO Int Req IOSW 0 D1 D2 D3 D4 D6 D7 D0 D5 IOSWIN P44 IOSW 1 SIOSF SIO Status D1 D2 D3 D4 D6 D7 D0 D5 D1 D2...

Page 74: ...by reading the SIOR Note When external clock is used the frequency should be less than 1MHz and recommended duty is 50 If both transmission mode is selected and transmission is performed simultaneous...

Page 75: ...a baud rate can also be defined by dividing clocks input to the ACLK pin The UART driver consists of RXR TXR ASIMR ASISR and BRGCR register Universal asynchronous serial I O mode UART can be selected...

Page 76: ...annot be written The RESET input sets RXR to 00H Receive shift register This register converts serial data input via the RXD pin to paralleled data When one byte of data is received at this register c...

Page 77: ...10 Odd parity 11 Even parity UART Tx Rx Enable bit R W 0 Receive Completion Interrupt Control When Error occurs 1 Receive completion interrupt request is not issued when an error occur No parity dete...

Page 78: ...ISR OVE R R R 0 No Frame error 1 Framing errorNote1 stop bit not detected UART Parity Error Flag PE UART Overrun Error Flag 0 No overrun error 1 Overrun errorNote2 0 No parity error 1 Parity error Tra...

Page 79: ...1 TPS0 R W UART Source Clock Selection for 5 bit count 000 ACLK 001 fXIN 2 010 fXIN 4 011 fXIN 8 100 fXIN 16 101 fXIN 32 110 fXIN 64 111 fXIN 128 UART Input Clock Selection 0000 fSCK 16 0001 fSCK 17 0...

Page 80: ...e data in which the error oc curred is still transferred to RXR When ASIMR bit 1 IS RM is cleared to 0 upon occurrence of an error and INT_RX occurs When ISRM bit is set to 1 INT_RX does not occur in...

Page 81: ...00 7AH 0 16 6AH 0 16 1200 7AH 0 16 6AH 0 16 5AH 0 16 2400 72H 0 00 70H 1 73 6AH 0 16 5AH 0 16 4AH 0 16 4800 62H 0 00 60H 1 73 5AH 0 16 4AH 0 16 3AH 0 16 9600 52H 0 00 50H 1 73 4AH 0 16 3AH 0 16 2AH 0...

Page 82: ...is shown below fBUZ Buzzer frequency fXIN Oscillator frequency Divide Ratio Prescaler divide ratio by BUCK 1 0 BUR Lower 6 bit value of BUZR Buzzer period value The frequency of output signal is cont...

Page 83: ...72 3 125 2 841 2 604 2 404 2 232 2 083 1 953 28 29 2A 2B 2C 2D 2E 2F 6 098 5 952 5 814 5 682 5 556 5 435 5 319 5 208 3 049 2 976 2 907 2 841 2 778 2 717 2 660 2 604 1 524 1 488 1 453 1 420 1 389 1 359...

Page 84: ...ive timer counter register The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register The AD converter Interrupt is generated by ADCIF which is set by f...

Page 85: ...bles all interrupts at once Figure 18 2 Interrupt Enable Flag Register Reset Interrupt Symbol Priority Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt...

Page 86: ...m status word are saved pushed onto the stack area The stack pointer decreases 3 times 4 The entry address of the interrupt service program is read from the vector table address and the entry address...

Page 87: ...Also when multiple interrupt services are nested it is necessary to avoid using the same data memory area for saving registers The following method is used to save restore the general purpose register...

Page 88: ...different priority levels are received si multaneously the request of higher priority level is ser viced If requests of the interrupt are received at the same time simultaneously an internal polling...

Page 89: ...ble INT0 only LDM IENL 0 Disable other int EI Enable Interrupt LDM IENH 0FFH Enable all interrupts LDM IENL 0FFH POP Y POP X POP A RETI enable INT0 TIMER 1 service INT0 service Main Program service Oc...

Page 90: ...0001B Response Time The INT0 INT3 edge are latched into INT0IF INT3IF at every machine cycle The values are not actually polled by the circuitry until the next machine cycle If a request is active and...

Page 91: ...ESS 0F8H PSR0 EC0E INT0E INT2E INT3E 0 R12 1 INT1 0 R03 1 INT2 0 R00 1 INT3 0 R11 1 PWM3O 0 R07 1 EC1 0 R04 1 EC0 LSB MSB BTCL W W W W W W W W IED2H IED3L IED3H IED0H INITIAL VALUE 00H ADDRESS 0EEH IE...

Page 92: ...AM Interrupts allow both on chip RAM and Control registers to retain their values If I flag 1 the normal interrupt response takes place If I flag 0 the chip will resume execution starting with the ins...

Page 93: ...ss of the instruction to be executed after the instruction STOP which starts the STOP operating mode Note The Stop mode is activated by execution of STOP instruc tion after setting the SSCR to 5AH Thi...

Page 94: ...th on chip RAM and Control registers to retain their values If I flag 1 the normal interrupt response takes place If I flag 0 the chip will resume execution starting with the instruction following the...

Page 95: ...FLAG 1 Interrupt Service Routine Next INSTRUCTION 0 Master Interrupt Enable Bit PSW 2 Corresponding Interrupt Enable Bit IENH IENL Before executing Stop instruction Basic Interval Timer must be set Os...

Page 96: ...both on chip RAM and Control registers to retain their values If I flag 1 the normal interrupt response takes place In this case if the bit WDTON of CKCTLR is set to 0 and the bit WDTE of IENH is set...

Page 97: ...N pin N 1 N N 2 00 01 FE FF 00 00 N 1 N 2 Clear Basic Interval Timer STOP Instruction Execution Normal Operation Stabilization Time tST 20mS Internal Clock External Interrupt BIT Counter Internal RC C...

Page 98: ...e level by approximately 0 3V a current begins to flow Therefore if cutting off the output transistor at an I O port puts the pin signal into the high impedance state a current flow across the ports i...

Page 99: ...DD is applied to input pin there can be little current max 1mA at around 2V flow If it is not appropriate to set as an input mode then set to output mode considering there is no current flow The port...

Page 100: ...to a Schmitt Trigger A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods within the operating voltage range and oscillation stable it is applied and the internal st...

Page 101: ...ternal noise which could not be returned to normal operation and would become malfunction state If the CPU tries to fetch the instruction from ineffective code area or RAM area the address fail reset...

Page 102: ...experiment with it Therefore af ter final development of user program this function may be experimented or evaluated Figure 21 1 Power Fail Voltage Detector Register Figure 21 2 Example S W of Reset f...

Page 103: ...ar 2005 Ver 0 2 99 Figure 21 3 Power Fail Processor Situations at 4MHz operation Internal RESET Internal RESET Internal RESET VDD VDD VDD VPFDMAX VPFDMIN VPFDMAX VPFDMIN VPFDMAX VPFDMIN 65 5mS 65 5mS...

Page 104: ...en the high frequency noise is continuing Change system clock to the internal oscillation clock when the XIN XOUT is shorted or opened the main oscillation is stopped except by stop instruction and th...

Page 105: ...ernal clock source when the external clock is recovered to normal state IN4 2 MCLK CLKXO XO Option The IN4MCLK XO IN2MCLK XO bit of the De vice Configuration Area MASK option for MC80C0104 0204 enable...

Page 106: ...l 2MHz Oscillation R33 R34 Enable CLK2 ONP OFP LOCK POR R35EN CLK1 CLK0 010 EXRC External R RC Oscillation R34 Enable 011 X tal Crystal or Resonator Oscillation 100 IN4MCLKXO internal 4MHz Oscillation...

Page 107: ...s ONP Enable OSC Noise Protector ONP Operation En Disable Bit No ONP Disable OFP Yes Enables Oscillation Fail Processor ONP clock changer Change the Inter clock when oscillation failed No Disables Osc...

Page 108: ...MC80F0104 0204 Preliminary 104 Mar 2005 Ver 0 2 25 Emulator EVA Board Setting...

Page 109: ...eset by external user tar get board ON Reset is available by either user target system board or Emulator RESET switch OFF Reset the MCU by Emulator RESET switch Does not work from user target board 5...

Page 110: ...select the R34 or XOUT switch 5 6 These switches select the R35 or Reset This switch select the Normal I O port off or special function select on ON OFF R33 R34 R35 Port selected OFF ON XIN XOUT Rese...

Page 111: ...arget board and the COM port of your PC 2 Configure the COM port of your PC as following 3 Turn your target B D power switch ON Your target B D must be configured to enter the ISP mode 4 Run the Magna...

Page 112: ...ected Option Write Progam the configuration data of target MCU The security locking is performed with this button Option Set the configuration data of target MCU The security locking is set with this...

Page 113: ...of additional expense in components and circuit board area The boot loader can be executed by holding ALE high RESET VPP as 9V and ACLK with the OSC 1 8432MHz The ISP function uses five pins TxD RxD A...

Page 114: ...CON1 Female DB9 J2 VSS VDD J3 External VDD RESET VPP MCU_TxD MCU_RxD VDD VSS 10uF 16V 0 1uF MAX232 ACLK_CLK Vcc Out Gnd OSC X1 1 8432MHz 22 0 1uF 100 The ragne of VDD must be from 4 5 to 5 5V and ISP...

Page 115: ...APPENDIX...

Page 116: ......

Page 117: ...DAS 111 EI LDM dp imm STA dp STA dp X STA abs TAX STY dp TCALL 14 STC M bit STX dp STX dp Y XAX STOP LOW HIGH 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19...

Page 118: ...2 5 20 ASL abs 18 3 5 21 CMP imm 44 2 2 Compare accumulator contents with memory contents 22 CMP dp 45 2 3 A M 23 CMP dp X 46 2 4 24 CMP abs 47 3 4 N ZC 25 CMP abs Y 55 3 5 26 CMP dp X 56 2 6 27 CMP...

Page 119: ...OR imm 64 2 2 Logical OR 65 OR dp 65 2 3 A A M 66 OR dp X 66 2 4 67 OR abs 67 3 4 N Z 68 OR abs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 72 ROL A 28 1 2 Rotate left through carry 73...

Page 120: ...25 STA X F4 1 4 26 STA X FB 1 4 X register auto increment M A X X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 M X 29 STX abs FC 3 5 30 STY dp E9 2 4 Store Y register con...

Page 121: ...BIT dp 0C 2 4 Bit test A with memory MM Z 4 BIT abs 1C 3 5 Z A M N M7 V M6 5 CLR1 dp bit y1 2 4 Clear bit M bit 0 6 CLRA1 A bit 2B 2 2 Clear A bit A bit 0 7 CLRC 20 1 2 Clear C flag C 0 0 8 CLRG 40 1...

Page 122: ...el 10 2 2 4 Branch if minus if N 0 then pc pc rel 11 BRA rel 2F 2 4 Branch always pc pc rel 12 BVC rel 30 2 2 4 Branch if overflow bit clear if V 0 then pc pc rel 13 BVS rel B0 2 2 4 Branch if overflo...

Page 123: ...1 1 4 NOP FF 1 2 No operation 5 POP A 0D 1 4 sp sp 1 A M sp 6 POP X 2D 1 4 sp sp 1 X M sp 7 POP Y 4D 1 4 sp sp 1 Y M sp 8 POP PSW 6D 1 4 sp sp 1 PSW M sp restored 9 PUSH A 0E 1 4 M sp A sp sp 1 10 PU...

Page 124: ...viii Mar 2005 Ver 0 2 MC80F0104 0204 Preliminary...

Page 125: ...n Date YYYY MM DD Approval Date YYYY MM DD Please confirm our verification data I agree with your verification data and confirm you to make mask set Check Sum Tel Fax Name Signature Tel Fax Name Signa...

Page 126: ...n Date YYYY MM DD Approval Date YYYY MM DD Please confirm our verification data I agree with your verification data and confirm you to make mask set Check Sum Tel Fax Name Signature Tel Fax Name Signa...

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