MagnaChip MC80F0104, User Manual, Page: 45 / 126

Preliminary MC80F0104/0204
Mar. 2005 Ver 0.2 41
12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state. The watchdog timer
signal for detecting malfunction can be selected either a re-
set CPU or a interrupt request.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
The watchdog timer has two types of clock source. The
first type is an on-chip RC oscillator which does not re-
quire any external components. This RC oscillator is sepa-
rate from the external oscillator of the X
IN
pin. It means
that the watchdog timer will run, even if the clock on the
X
IN
pin of the device has been stopped, for example, by en-
tering the STOP mode. The other type is a prescaled sys-
tem clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
Watchdog timer interrupt or reset the CPU in accordance
with the bit WDTON.
Note:
Because the watchdog timer counter is enabled after clear-
ing Basic Interval Timer, after the bit WDTON set to "1", maximum
error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
WDTR) and the WDTCL is cleared automatically after 1 machine
cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
LDM CKCTLR,#3FH; enable the RC-OSC WDT
LDM WDTR,#0FFH ; set the WDT period
LDM SSCR, #5AH ;ready for STOP mode
STOP ; enter the STOP mode
NOP
NOP ; RC-OSC WDT running
:
The RC-WDT oscillation period is vary with temperature,
V
DD
and process variations from part to part (approxi-
mately, 33~100uS). The following equation shows the
RCWDT oscillated watchdog timer time-out.
T
RCWDT
=CLK
RCWDT
×2
8
×
WDTR + (CLK
RCWDT
×2
8)
/2
where, CLK
RCWDT
= 33~100uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
T
WDT
= (WDTR+1)
×
Interval of BIT
Figure 12-1 Block Diagram of Watchdog Timer
to reset CPU
BASIC INTERVAL TIMER
Count
enable
Watchdog
7-bit compare data
comparator
Watchdog Timer interrupt
clear
clear
WDTIF
Counter (7-bit)
WDTCL
“0”
“1”
WDTON in CKCTLR [0F2
H
]
OVERFLOW
Watchdog Timer
Register
WDTR
Internal bus line
7
[0F4
H
]
source