11
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if
both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin
goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To
re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
Summary of Contents for MX25L4006E
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