Logitek ULTRA-VU, Operation & Service Manual

Page: 11 / 29

The input data signal is connected to pulse trans-
former T1 via DC blocking capacitor C5. The output of
T1 is loaded by R1,R2, R3 and connected to data re-
ceiver IC1. C1 and R4 form a loop filter used by IC1 to
recover the embedded clock from the coded input
signal. IC1 separates the audio data, channel data
and clock from the input data. The audio is sent to the
DSP in 64 bit strings via a serial port. Three other sig-
nals from IC1 are read once per stereo sample and
are connected to the DSP’s parallel data port via iso-
lation resistors R9. These are the channel status bit,
start of subcode data block flag and receiver error
flag. These are input to the DSP via a read to address
zero.
Connector P5 attaches to the DSP’s other serial
port and allows analog data to be sent to the DSP via
an external ADC card. The connector also provides
power and the master processor clock for use by the
ADC card.
If the digital receiver IC1 can lock onto an input sig-
nal then the DSP will display that signal whether it
contains errors or not. If no signal is connected to J1
or the data rate is out of the receiver’s capture range,
then the DSP will display the data from P5. This hap-
pens even if nothing is connected to the analog in-
puts or the ADC card is absent.
4-8 Display Assembly LG-267
Filtered power is connected to the driver card via
P1. +5VDC regulator IC6 is bolted to the meter enclo-
sure to increase heat dissipation and connects to the
driver card via P2. C4 provides bulk power storage
while C1, C2, C3 and C5 through C8 stabilize the 5
volt supply.
Each display driver IC controls 64 LEDs by scan-
ning them in an eight by eight matrix. Segment lines
are current controlled and connect to the LED an-
odes. Digit lines connect to the LED cathodes. Scan-
ning is accomplished by taking each digit line low one
at a time and sourcing current from the segment lines
for whichever of the 8 LEDs in a digit group need to be
lit. The driver chips can also selectively decode BCD
data into 7-segment numeric display signals. Maxi-
mum LED brightness is set by the external resistors.
The drivers further control brightness by pulse-width
modulating the LED on times with a value supplied by
the DSP.
The display drivers accept synchronous serial
data (clock, data, load) in 16 bit strings composed of
an address byte and a data byte. The driver ICs are
arranged in two chip groups. The data out of one chip
is hooked to the data in of the second chip such that 4
bytes can be loaded, two to each chip, with one load
pulse.
IC1 and IC2 drive the upper bargraph (left chan-
nel). IC3 and IC4 drive the lower bargraph (right
channel). IC5 drives the scale indicator LEDs along
the bottom edge of the display.
Avoid removing all three LED alignment plates if at
all possible. There is very little space around the indi-
cator LEDs and, if any get bent, it can take some time
to reassemble the alignment plate. If a LED needs re-
placing, pry it out of its socket with a screwdriver and
remove it. Remember to consult the component dia-
gram for the correct orientation before installing a
new LED. Also note that the tricolor LEDs are graded
according to color and brightness. A sticker on the
back of the PCB denotes the correct lot number
needed for reordering.
4-9 ADC Input Card LG-264
The audio from the left input 1/4" phone connector
J2 is connected to a RF lowpass filter formed by R10,
R11, C3 and C4. The resistors also form a -9 dB pad
with the input impedance of the balanced receiver
IC4. IC4 provides an additional -6 dB pad between its
input and output. These pads allow +20 dBu input sig-
nals to be handled by the +/- 5 volt supply rails. The
output of IC4 is unity gain inverted by op-amp IC2b
and fed back to the reference input of IC4. This en-
ables IC4 to present an identical resistive load on its
two input pins. Input gain is adjusted via trimpot R9
which is the feedback resistor around gain stage
IC1b.
* * * * * * * * * IMPORTANT * * * * * * * * * *
Only replace IC2 with an op-amp which is slower
than the SSM2143 such as the TL072 used here. A
faster op-amp like the NE5532 will cause the output
of IC4 to oscillate.
* * * * * * * * * * * * * * * * * * * * * * * * * * * *
Signal from IC1b is fed through antialias filter R14
C8 and DC isolated by C11 before connecting to the
left input of the sigma delta analog to digital converter
IC7. The right channel connects to the converter via
similar circuitry.
The 12.288 MHz master clock input to the ADC is
generated by a crystal oscillator located on the DSP
control card. Combined left and right audio data is
sent synchronously (data, clock, frame sync) to the
DSP in 64-bit strings via connector P3. The reset sig-
nal from the DSP control card is also connected to the
ADC. The DSP activates the reset once a day which
causes the ADC to perform a self calibration routine
for about half a second. If the meter has undergone a
substantial temperature change, it may generate
noise up to -70 dBFS until it undergoes a calibration
cycle
The three supply voltages from P3 are EMI iso-
lated by ferrite beads FR1, FR2 and FR3 before con-
necting to the other circuitry. IC5 and IC6 supply low
noise reg/- 5 VDC to the analog portions of
the circuit. The digital part of the data converter gets
its +5 VDC from the DSP control card.
Page 11 ** Ultra-VU Operation & Service Manual **