LTC3875
31
3875fb
For more information
www.linear.com/LTC3875
APPLICATIONS INFORMATION
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV
CC
to ground. The resulting dQ/dt is a cur-
rent out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
=
f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTV
CC
power through EXTV
CC
from an
output-derived source will scale the V
IN
current required
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). For example, in a 20V to 5V applica-
tion, 10mA of INTV
CC
current results in approximately
2.5mA of V
IN
current. This reduces the midcurrent loss
from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor (if used). In continuous mode, the average output
current flows through L, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be
summed with the resistances of L to obtain I
2
R losses.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional efficiency
degradation in portable systems. It is very important to
include these “system” level losses during the design
phase. The internal battery and fuse resistance losses can
be minimized by making sure that C
IN
has adequate charge
storage and very low ESR at the switching frequency. The
LTC3875 2-phase architecture typically halves this input
capacitance requirement over competing solutions. Other
losses including Schottky conduction losses during dead
time and inductor core losses generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to
∆
I
LOAD (ESR)
, where ESR is the effective
series resistance of C
OUT
.
∆
I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I
TH
external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications. The I
TH
series R
C
-C
C
filter sets the dominant pole-zero loop compensation.
The values can be modified slightly (from 0.5 to 2 times
their suggested values) to optimize transient response
once the final PC layout is done and the particular output
capacitor type and value have been determined. The output
capacitors need to be selected because the various types
and values determine the loop gain and phase. An output
current pulse of 20% to 80% of full-load current having a
rise time of 1µs to 10µs will produce output voltage and
I
TH
pin waveforms that will give a sense of the overall
loop stability without breaking the feedback loop. Placing
