background image

LTC3875

15

3875fb

For more information 

www.linear.com/LTC3875

(see Figure 4b for inductor DCR sensing connections). The 

filter time constant, R1 • C1, of the SNSD

+

 should match the 

L/DCR of the output inductor, while the filter at SNSA

+

 should 

have a bandwidth of five times larger than that of SNSD

+

,  

i.e, R2 • C2 equals one-fifth of R1 • C1.

Thermal Balancing For Multiphase Operation

When  LTC3875  is  used  as  a  single  output  multiphase 

converter, the temperature of the whole system can be 

balanced by enabling the thermal balancing function. This 

prevents hot spots due to imperfection of current match-

ing and component mismatch. Therefore, it improves the 

overall reliability of the power supply system. 
Refer to Figure 2 for the following discussion of thermal 

balancing for the LTC3875.

The  thermal  balancing  can  be  enabled  by  setting  the 

ENTMPB pin to ground. Each channel has a TCOMP/ITEMP 

pin which sources a 30µA precision current. By connecting 

a  linearized  NTC  network  or  a  temperature  sensing  IC 

placed near the hot spot of the converter from this pin to 

SGND, the temperature of each channel can be sensed. 

The sensed voltage from each channel is converted to a 

current, which is programmable with resistor, R

TCOMP

at the TRSET pin. The current from each channel is then 

summed together at the TAVG pin. The resistor value at 

the TAVG is R

TCOMP

/n, where n is the number of phases. 

The voltage at TAVG is then a representation of the average 

temperature  of  the  whole  system.  By  comparing  the 

phase temperature and average temperature, an internal 

transconductance amplifier then adjusts the phase current 

accordingly to match the phase temperature to the average 

temperature of the system. 

OPERATION

+

+

R

TCOMP

R

AVG

TRSET1

CHANNEL 1

CHANNEL 2

TAVG

TRSET2

REPEAT FOR

MULTICHIP

OPERATIONS

MIRROR

1:1

THERMAL

SENSOR

OR NTC

30µA

TCOMP1

ADJUST

CHANNEL

CURRENT

g

m

AMP

+

+

R

TCOMP

3875 F02

MIRROR

1:1

THERMAL

SENSOR

OR NTC

30µA

TCOMP2

ADJUST

CHANNEL

CURRENT

g

m

AMP

Figure 2. Thermal Balancing Technique for Multichip Operations

Summary of Contents for LTC3875

Page 1: ...ng Differential Amplifiers n Optional Fast Transient Operation n Phase Lockable Fixed Frequency 250kHz to 720kHz n Dual 180 Phased Controllers Reduce Required Input Capacitance and Power Supply Induce...

Page 2: ...N2 IFAST ENTMPB PGOOD SW2 21 30 10 1 TJMAX 125 C JA 33 C W JC 2 0 C W EXPOSED PAD PIN 41 IS SGND PGND MUST BE SOLDERED TO PCB MODE PLLIN ILIM FREQ IFAST ENTMPB VOSNS s VOSNS s Voltages INTVCC to 0 3V...

Page 3: ...TRMPBF suffix ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage Range 4 5 38 V VOUT Output Voltage Range SNSD Pin to VOUT SNSD Pin to GND 0...

Page 4: ...VSNS s 1 2V ILIM 3 4 INTVCC VSNS s 1 2V ILIM INTVCC l l l l l 45 70 95 117 5 142 5 50 75 100 125 150 55 80 105 132 5 157 5 mV mV mV mV mV IMISMATCH Channel to Channel Current Mismatch ILIM Float ENTM...

Page 5: ...ull Down RDS ON BG Low 1 1 Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device Exposure to any Absolute Maximum Rating condition for extended pe...

Page 6: ...LOAD CURRENT A 30 EFFICIENCY 90 100 20 10 80 50 70 60 40 0 01 1 10 100 3875 G02 0 0 1 Burst Mode OPERATION CCM VIN 12V VOUT 1V PULSE SKIPPING ILOAD 40A DIV 5A TO 30A VOUT 100mV DIV AC COUPLED 10 s DI...

Page 7: ...3 4 INTVCC ILIM INTVCC VSENSE COMMON MODE VOLTAGE V 0 20 25 35 3 3875 G12 15 10 1 2 4 5 0 30 CURRENT SENSE THRESHOLD mV ILIM INTVCC ILIM 3 4 INTVCC ILIM 1 2 INTVCC ILIM 1 4 INTVCC ILIM GND FEEDBACK V...

Page 8: ...3875 G18 3 4 4 6 4 8 4 2 100 150 RISING FALLING INPUT VOLTAGE V 0 OSCILLATOR FREQUENCY kHz 500 600 700 40 3875 G19 400 300 200 0 10 20 30 100 900 VFREQ INTVCC VFREQ 1 22V VFREQ GND 800 INPUT VOLTAGE...

Page 9: ...e frequency of the internal oscillator IFAST Pin 17 Programmable Pin for Fast Transient Op eration for Channel 2 Only A resistor to ground programs the threshold of the output load transient excursion...

Page 10: ...urrents These currents are then mirrored to pin TAVG and are added together for all channels Float this pin if thermal balancing is not used TCOMP1 ITEMP1 TCOMP2 ITEMP2 Pin 37 Pin 12 Input of the Temp...

Page 11: ...REG ACTIVE CLAMP OSC 5k MODE SYNC DETECT SLOPE COMPENSATION UVLO MIRROR 1 50k ITHB 1 A 5 5 A FREQ CLKOUT MODE PLLIN IFAST CHANNEL 2 ONLY PHASMD TCOMP ITEMP 0 6V BURST EN EXTVCC ILIM ICMP IREV F 4 7V F...

Page 12: ...to VOUT the loop may enter dropout and attempt to turn on the top MOSFET continuously The dropout detector detects this and forces the top MOSFET off for about one twelfth of the clock period plus 100...

Page 13: ...d for Burst Mode operation the inductor current is not allowed to reverse The reverse current comparator IREV turns off the bottom external MOSFET just before the inductor current reaches zero prevent...

Page 14: ...route the VOSNS and VOSNS PCB traces parallel to each other all the way to the remote sensing points on the board In addition avoid routing these sensitive traces nearanyhighspeedswitchingnodesintheci...

Page 15: ...Aprecisioncurrent Byconnecting a linearized NTC network or a temperature sensing IC placed near the hot spot of the converter from this pin to SGND the temperature of each channel can be sensed The s...

Page 16: ...network with regular OPERATION resistors Consult the NTC manufacturer s data sheets for detailed information Another use for the TCOMP ITEMP pins in addition to NTC compensated DCR sensing is adjustin...

Page 17: ...oring the ripple voltage will compare with the scaled version of the programmed window voltage and trip This indicates that a load step is detected The LTC3875 will immedi ately turn on the top gate a...

Page 18: ...sholds of 15mV or 25mV The user should select the proper ILIM level based on the inductor DCR value and targeted current limit level SNSD SNSA and SNS Pins The SNSA and SNS pins are the direct inputs...

Page 19: ...is capableofsensingthesignalofaninductorDCRinthesub milliohm range Figure 4b The DCR is the inductor DC winding resistance which is often less than 1m for high current inductors In high current and lo...

Page 20: ...0nA respectively and it causes some small error to the sense signal There will be some power loss in R1 and R2 that relates to the duty cycle and will be the most in continuous mode at the maximum inp...

Page 21: ...equations which will be the point where the curves intersect Once RP is known solve for RS The resistance of the NTC thermistor can be obtained from the vendor s data sheet either in the form of grap...

Page 22: ...xcess of 40 Normally this re sults in a reduction of maximum inductor peak current for duty cycles 40 However the LTC3875 uses a scheme that counteracts this compensating ramp which allows the maximum...

Page 23: ...ET manufacturers have designed special purposedevicesthatprovidereasonablylowon resistance with significantly reduced input capacitance for the main switch application in switching regulators The peak...

Page 24: ...conduction of the two large power MOSFETs This pre vents the body diode of the bottom MOSFET from turning on storing charge during the dead time and requiring a reverse recoveryperiodwhichcouldcostas...

Page 25: ...lave channel In practice though either phase can be used as the master To implement the coincident tracking in Figure 9a con nect an additional resistive divider to VOUT1 and connect its midpoint to t...

Page 26: ...nt interaction between the channels High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi mum junction temperature rating for the LTC3875 to be...

Page 27: ...MAX When adjusting the gate drive level the final arbiter is the total input current for the regulator If a change is made and the input current decreases then the efficiency has improved If there is...

Page 28: ...dequate for the dual controller design Also the input protection fuse resistance battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2 phase...

Page 29: ...hutdown is set for approximately 160 C with 10 C of hysteresis When the chip reaches 160 C both TG and BG are disabled until the chip cools down below 150 C Phase Locked Loop and Frequency Synchroniza...

Page 30: ...switching noise in the voltage and current loop As the peak sense voltage decreases the minimum on time gradually increases to 110ns This is of particular concern in forced continuous applications wi...

Page 31: ...es during the design phase The internal battery and fuse resistance losses can beminimizedbymakingsurethatCIN hasadequatecharge storage and very low ESR at the switching frequency The LTC3875 2 phase...

Page 32: ...rethetopN channelMOSFETsM1andM3locatedwithin 1cm of each other with a common drain connection at CIN Do not attempt to split the input decoupling for the two channels as it can cause a large resonant...

Page 33: ...nt Waveforms Figure 14 Recommended Printed Circuit Layout Diagram CB2 CB1 CINTVCC 4 7 F CIN D1 OPT 10 F 2 CERAMIC M1 M2 M3 M4 D2 OPT CVIN 1 F VIN 1 F RIN 2 2 L1 L2 COUT1 VOUT1 GND VOUT2 3875 F14 COUT2...

Page 34: ...CB implementation Variation in the duty cycle at a sub harmonicratecansuggestnoisepickupatthecurrent or voltage sensing inputs or inadequate loop compensa tion Overcompensation of the loop can be used...

Page 35: ...nsingisusedinthiscircuit IfC1andC2arechosen to be 220nF based on the chosen 0 33 H inductor with 0 32m DCR R1 and R2 can be calculated as R1 L DCR C1 4 69k R2 L DCR C2 5 937 INTVCC INTVCC INTVCC 4 7 F...

Page 36: ...S RDS ON 1 1m is chosen for the bottom FET The resulting power loss is PSYNC 20V 1 5V 20V 30A 2 1 0 005 75 C 25 C 0 001 PSYNC 1 14W CIN is chosen for an equivalent RMS current rating of at least 13 7A...

Page 37: ...0NE2LSI 31 32 33 34 35 36 37 38 39 40 ITH C11 100pF R19 10k C12 1 5nF V OSNS V OSNS TAVG TRSET2 TCOMP2 TAVG TRSET2 TCOMP2 TRSET1 TRSET2 TAVG FREQ RUN2 RUN IFAST ENTMPB PGOOD 3875 F17a V FB TK SS C IN4...

Page 38: ...18 19 C20 0 1 F D4 D3 CMDSH 3 R21 2 2 CMDSH 3 Q7 BSC010NE2LSI Q6 BSC050NE2LS Q5 BSC010NE2LSI 31 32 33 34 35 36 37 38 39 40 ITH C17 100pF V OSNS TAVG TRSET2 TCOMP2 TAVG TRSET4 TCOMP4 TRSET3 TRSET4 FREQ...

Page 39: ...4 BSC010NE2LSI Q3 BSC024NE2LS Q2 BSC010NE2LSI 31 32 33 34 35 36 37 38 39 40 ITH C11 100pF R19 20k C12 2 2nF V OSNS V OSNS TAVG TRSET2 TCOMP2 TAVG TRSET2 TCOMP2 TRSET1 TRSET2 TAVG FREQ RUN2 RUN IFAST E...

Page 40: ...0pF R19 10k C12 1 5nF V OSNS V OSNS TAVG TRSET2 TCOMP2 TAVG TRSET2 TCOMP2 FREQ RUN2 RUN IFAST ENTMPB PGOOD 3875 F19 V FB TK SS C16 47nF R32 100k 1 C2 0 1 F C19 47nF 1 R13 13 3k R14 20k R16 10 C4 47nF...

Page 41: ...S 31 32 33 34 35 36 37 38 39 40 C11 10pF R19 174k C12 220pF V O1SNS V O1SNS TAVG TRSET2 TCOMP2 TAVG TRSET2 TCOMP2 TRSET1 TRSET2 TAVG FREQ RUN2 IFAST ENTMPB PGOOD C21 0 1 F V IN C IN5 10 F 1210 R32 100...

Page 42: ...R19 10k C12 1 5nF V O1SNS V O1SNS TAVG TRSET2 TCOMP2 TAVG TRSET2 TCOMP2 FREQ RUN2 IFAST ENTMPB PGOOD C21 0 1 F R32 100k 1 C2 0 1 F C19 220nF 1 R13 13 3k R14 20k R10 1k R9 3 01k C4 220nF C3 220nF C13...

Page 43: ...ALL BE SOLDER PLATED 5 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6 DRAWING NOT TO SCALE PIN 1 TOP MARK SEE NOTE 5 PIN 1 NOTCH R 0 30 TYP OR 0 35 45 CHAMFER 0...

Page 44: ...AND BOTTOM OF PACKAGE PIN 1 TOP MARK SEE NOTE 6 PIN 1 NOTCH R 0 45 OR 0 35 45 CHAMFER 0 40 0 10 40 39 1 2 BOTTOM VIEW EXPOSED PAD 4 50 REF 4 SIDES 4 42 0 10 4 42 0 10 4 42 0 05 4 42 0 05 0 75 0 05 R...

Page 45: ...itsuse LinearTechnologyCorporationmakesnorepresenta tion that the interconnection of its circuits as described herein will not infringe on existing patent rights REVISION HISTORY REV DATE DESCRIPTION...

Page 46: ...4V VIN 60V 0 8V VOUT 24V IQ 50 A LTC3861 LTC3861 1 Dual Multiphase Synchronous Step Down Voltage Mode DC DC Controller with Diff Amp and Accurate Current Sharing Operates with DrMOS Power Blocks or E...

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