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10

LTC3736

3736fa

Main Control Loop

The LTC3736 uses a constant frequency, current mode
architecture with the two controllers operating 180 de-
grees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (I

CMP

) resets the latch. The

peak inductor current at which I

CMP

 resets the RS latch is

determined by the voltage on the I

TH

 pin, which is driven

by the output of the error amplifier (EAMP). The V

FB

 pin

receives the output voltage feedback signal from an exter-
nal resistor divider. This feedback signal is compared to
the internal 0.6V reference voltage by the EAMP. When the
load current increases, it causes a slight decrease in V

FB

relative to the 0.6V reference, which in turn causes the I

TH

voltage to increase until the average inductor current
matches the new load current. While the top P-channel
MOSFET is off, the bottom N-channel MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the current reversal comparator, I

RCMP

, or the

beginning of the next cycle.

Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)

The LTC3736 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9

µ

A. The TG outputs are held high (off)

and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7

µ

A current source to charge

up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736’s two controllers are enabled.

The start-up of V

OUT1

 is controlled by the LTC3736’s

internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V

FB1

 to the internal

soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.

The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor C

SS

 between the

RUN/SS and SGND pins. As the RUN/SS pin continues to

OPERATIO

U

rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7

µ

A current source), the EAMP

regulates the V

FB1

 proportionally linearly from 0V to 0.6V.

The start-up of V

OUT2

 is controlled by the voltage on the

TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736 regulates
the V

FB2

 voltage to the TRACK pin instead of the 0.6V

reference. Typically, a resistor divider on V

OUT1

 is con-

nected to the TRACK pin to allow the start-up of V

OUT2

 to

“track” that of V

OUT1

. For one-to-one tracking during start-

up, the resistor divider would have the same values as the
divider on V

OUT2 

that is connected to V

FB2

.

Light Load Operation (Burst Mode or Continuous
Conduction) (SYNC/FCB Pin)

The LTC3736 can be enabled to enter high efficiency Burst
Mode operation or forced continuous conduction mode at
low load currents. To select Burst Mode operation, tie the
SYNC/FCB pin to a DC voltage above 0.6V (e.g., V

IN

). To

select forced continuous operation, tie the SYNC/FCB to a
DC voltage below 0.6V (e.g., SGND). This 0.6V threshold
between Burst Mode operation and forced continuous mode
can be used in secondary winding regulation as described
in the Auxiliary Winding Control Using SYNC/FCB Pin dis-
cussion in the Applications Information section.

When a controller is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the I

TH

 pin indicates a lower value. If the average inductor

current is lower than the load current, the EAMP will
decrease the voltage on the I

TH

 pin. When the I

TH

 voltage

drops below 0.85V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.

In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3736 draws.
The load current is supplied by the output capacitor. As
the output voltage decreases, the EAMP increases the I

TH

voltage. When the I

TH

 voltage reaches 0.925V, the SLEEP

signal goes low and the controller resumes normal
operation by turning on the external P-channel MOSFET
on the next cycle of the internal oscillator.

(Refer to Functional Diagram)

Summary of Contents for No Rsense LTC3736

Page 1: ...ent mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency Power loss and noise due to the ESR of the input capacitance are minimized by operating th...

Page 2: ...N PACKAGE 24 LEAD PLASTIC SSOP 24 23 22 21 20 19 18 17 16 15 14 13 SW1 IPRG1 VFB1 ITH1 IPRG2 PLLLPF SGND VIN TRACK VFB2 ITH2 PGOOD SENSE1 PGND BG1 SYNC FCB TG1 PGND TG2 RUN SS BG2 PGND SENSE2 SW2 ORDE...

Page 3: ...0 5 VFB1 2 Input Current Note 5 10 50 nA TRACK Input Current TRACK 0 6V 10 50 nA Overvoltage Protect Threshold Measured at VFB 0 66 0 68 0 7 V Overvoltage Protect Hysteresis 20 mV Auxiliary Feedback T...

Page 4: ...ONTINUOUS MODE SYNC FCB 0V VIN 3 3V VOUT 1 8V ILOAD 200mA FIGURE 17 CIRCUIT 4 s DIV 3736 G05 PULSE SKIPPING MODE SYNC FCB 550kHz IL 1A DIV VIN 5V RLOAD1 RLOAD2 1 FIGURE 15 CIRCUIT 200 s DIV 3736 G06 5...

Page 5: ...vs Temperature Shutdown RUN Threshold vs Temperature RUN SS Pull Up Current vs Temperature Maximum Current Sense Threshold vs Temperature TEMPERATURE C 60 0 RUN SS VOLTAGE V 0 1 0 3 0 4 0 5 1 0 0 7 20...

Page 6: ...nected to VFB2 from VOUT2 should be used to connect to TRACK from VOUT1 PGOOD Pin 9 Pin 12 Power Good Output Voltage Moni tor Open Drain Logic Output This pin is pulled to ground when the voltage on e...

Page 7: ...ns19 13 Pins22 16 Bottom NMOS Gate Drive Output These pins drive the gates of the external N channel MOSFETs These pins have an output swing from PGND to SENSE SENSE1 SENSE2 Pins 21 11 Pins 24 14 Posi...

Page 8: ...HROUGH PGND TG1 SENSE1 VIN VOUT1 CIN COUT1 MP1 MN1 BG1 R1B L1 PGND VFB1 ITH1 RITH1 CITH1 0 6V 0 12V SC1 VFB1 SW1 SENSE1 R1A EXTSS INTSS EAMP SHDN BURSTDIS SLEEP1 0 3V IPROG1 ICMP 0 15V BURSTDIS VFB1 O...

Page 9: ...IREV2 S R RS2 ANTISHOOT THROUGH PGND SENSE2 TG2 SENSE2 VIN VOUT2 COUT2 MP2 MN2 BG2 R2B RTRACKB RTRACKA L2 PGND VFB2 ITH2 TRACK RITH2 CITH2 0 6V 0 12V SC2 TRACK VFB2 SW2 R2A VOUT1 EAMP BURSTDIS SLEEP2...

Page 10: ...citor CSS between the RUN SS and SGND pins As the RUN SS pin continues to OPERATIO U rise linearly from approximately 0 65V to 1 3V being charged by the internal 0 7 A current source the EAMP regulate...

Page 11: ...thresholdonVFB2 isbasedonthesmaller of 0 12V and a fraction of the voltage on the TRACK pin This also allows VOUT2 to start up and track VOUT1 more easily Note that if VOUT1 is truly short circuited O...

Page 12: ...e maximum value of VITH is typically about 1 98V so the maximum sense voltage allowed across the external P channel MOSFET is 125mV 85mV or 204mV for the three respective states of the IPRG pin The pe...

Page 13: ...itry Improvements in both conducted and radiatedEMIalsodirectlyaccrueasaresultofthereduced RMSinputcurrentandvoltage Significantcostandboard footprint savings are also realized by being able to use sm...

Page 14: ...on the ITH pin is internally clamped which limits the maximum current sense threshold VSENSE MAX to approximately 128mV when IPRG is floating 86mV when IPRG is tied low 213mV when IPRG is tied high Th...

Page 15: ...eration Shoot through between the P channel and N channel MOSFETs can most easily be spotted by monitoring the input supply current As the input supply voltage in creases iftheinputsupplycurrentincrea...

Page 16: ...ng the controller clamps the peak inductor current to approximately I V R BURST PEAK SENSE MAX DS ON 1 4 Thecorrespondingaveragecurrentdependsontheamount of ripple current Lower inductor values higher...

Page 17: ...N 2VOUT where IRMS IOUT 2 This simple worst case condition is commonly usedfordesignbecauseevensignificantdeviationsdonot offer much relief Note that capacitor manufacturers ripple current ratings are...

Page 18: ...y COUT is the output capacitance and IRIPPLE is the ripple current in the induc tor The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage Setting Output Volt...

Page 19: ...type that provides zero degrees phase shift between the external and internal oscillators This type of phasedetectordoesnotexhibitfalselocktoharmonicsof the external clock The output of the phase dete...

Page 20: ...Phase Locked to External Clock Auxiliary Winding Control Using SYNC FCB Pin The SYNC FCB can be used as an auxiliary feedback to provide a means of regulating a flyback winding output When this pin d...

Page 21: ...uceddownto2 4V Alsoshown is the effect on VREF Minimum On Time Considerations Minimumon time tON MIN isthesmallestamountoftime in which the LTC3736 is capable of turning the top P channel MOSFET on an...

Page 22: ...tional loss Checking Transient Response The regulator loop response can be checked by looking at the load transient response Switching regulators take several cycles to respond to a step in load curre...

Page 23: ...ack resistor divid ers ITH compensation networks and the SGND pin The power grounds consist of the terminal of the input and output capacitors and the source of the N channel MOSFET Eachchannelshouldh...

Page 24: ...IPRG2 IPRG1 VFB1 ITH1 SW1 RVIN 10 RITH2 15k CITH2 220pF CSS 10nF CIN 10 F 2 CVIN 1 F VIN 5V VIN CITH2B 100pF RITH1 15k CITH1 220pF CITH1A 100pF RFB1B 187k RFB1A 59k PGOOD VFB2 TRACK 25 ITH2 TG2 LTC37...

Page 25: ...ACKA 59k RFB2A 59k RFB2B 118k COUT2 22 F 2 COUT1 22 F 2 D1 VOUT1 2 5V 2A VOUT2 1 8V 2A 3736 F16 L1 L2 VISHAY IHLP 2525CZ 01 D2 Figure 17 2 Phase Synchronizable Dual Output Synchronous DC DC Converter...

Page 26: ...15k CITH1 220pF CITH1A 100pF RFB1B 187k RFB1A 59k PGOOD VFB2 TRACK 25 ITH2 TG2 LTC3736EUF PGND TG1 SYNC FCB BG1 PGND 22 21 20 19 18 17 16 15 14 13 12 11 10 23 24 1 2 3 4 5 9 8 7 6 SENSE1 MP1 MP2 L1 1...

Page 27: ...697 4 00 0 10 4 SIDES NOTE 1 DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO 220 VARIATION WGGD X TO BE APPROVED 2 ALL DIMENSIONS ARE IN MILLIMETERS 3 DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PAC...

Page 28: ...to 36V 5V and 3 3V LDOs Switching Regulator 5mm 5mm QFN or 28 Lead SSOP LTC3736 1 Dual 2 Phase No RSENSE Synchronous Controller with VIN 2 75V to 9 8V IOUT Up to 5A 4mm 4mm QFN Package Spread Spectrum...

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