LTM9004
20
9004fa
For more information
www.linear.com/LTM9004
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit. Note that
OF is high when an overflow or underflow has occurred
on either channel I or channel Q.
Table 3. Output Codes vs Input Voltage
INPUT
OF
D13 – D0
(OFFSET BINARY)
D13 – D0
(2’S COMPLEMENT)
Overvoltage
1
11 1111 1111 1111
01 1111 1111 1111
Maximum
0
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
Minimum
0
0
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
Undervoltage
1
00 0000 0000 0000
10 0000 0000 0000
Digital Output Modes
Figure 10 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters the digi-
tal output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full speed operation, the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the ADC parallel digital output can be
selected for offset binary or 2’s complement format. Note
that MODE controls both I and Q channels. Connecting
MODE to GND or 1/3 V
DD
selects straight binary output
format. Connecting MODE to 2/3 V
DD
or V
DD
selects 2’s
complement output format. An external resistive divider
can be used to set the 1/3 V
DD
or 2/3 V
DD
logic values.
Table 4 shows the logic states for the MODE pin.
Table 4. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0
Straight Binary
Off
1/3V
DD
Straight Binary
On
2/3V
DD
2’s Complement
On
V
DD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged on I-channel or Q-channel. Note
that both channels share a common OF pin. OF is disabled
when I-channel is in sleep or nap mode.
applicaTions inForMaTion
Figure 10. Digital Output Buffer
LTM9004
9004 F10
OV
DD
V
DD
V
DD
0.1µF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
