LTM9004
11
9004fa
For more information
www.linear.com/LTM9004
Supply Pins
V
CC1
(Pins G5, H2), V
CC2
(Pins C5, C8, K5, K8):
Analog
5V Supply for Mixer and First Amplifiers. The specified
operating range is 4.5V to 5.25V. The voltage on this pin
provides power for the mixer and amplifier stages only
and is internally bypassed to GND.
V
CC3
(Pins C9, C12, K9, K12):
Analog Supply for Second
Amplifiers. The specified operating range is 4.5V to 5.5V for
LTM9004-AA and LTM9004-AB. The specified operating
range is 2.7V to 3.5V for LTM9004-AC and LTM9004-AD.
V
CC3
is internally bypassed to GND.
V
DD
(Pins D14, F13, G13, J14):
Analog 3V Supply for the
ADC. The specified operating range is 2.7V to 3.6V. V
DD
is internally bypassed to GND.
OV
DD
(Pins D17, J17):
Positive Supply for the Digital
Output Drivers. The specified operating range is 0.5V to
3.6V. OV
DD
is internally bypassed to OGND.
GND (See Table for Pin Locations):
Analog Ground.
OGND (Pins C17, K17):
Digital Output Driver Ground.
Analog Inputs
RF (Pin E2):
RF Input Pin. This is a single-ended 50Ω
terminated input. No external matching network is required
for the high frequency band. An external series capacitor
(and/or shunt capacitor) may be required for impedance
transformation to 50Ω in the low frequency band from
700MHz to 1.5GHz (see Figure 4). If the RF source is not
DC blocked, a series blocking capacitor should be used.
Otherwise, damage to the IC may result.
LO (Pin H3):
Local Oscillator Input Pin. This is a single-
ended 50Ω terminated input. No external matching network
is required in the high frequency band. An external shunt
capacitor (and/or series capacitor) may be required for
impedance transformation to 50Ω for the low frequency
band from 700MHz to 1.5GHz (see Figure 6). If the LO
source is not DC blocked, a series blocking capacitor must
be used. Otherwise, damage to the IC may result.
CLKQ (Pin G14):
Q-Channel ADC Clock Input. The input
sample starts on the positive edge. Tie CLKQ and CLKI
together.
CLKI (Pin F14):
I-Channel ADC Clock Input. The input
sample starts on the positive edge. Tie CLKQ and CLKI
together.
I
+
_ADJ (Pin B1):
DC Offset Adjust Pin for I-Channel, + Line.
Source or sink current through this pin to trim DC offset.
I
–
_ADJ (Pin C1):
DC Offset Adjust Pin for I-Channel, – Line.
Source or sink current through this pin to trim DC offset.
Q
+
_ADJ (Pin K1):
DC Offset Adjust Pin for Q-Channel, + Line.
Source or sink current through this pin to trim DC offset.
Q
–
_ADJ (Pin L1):
DC Offset Adjust Pin for Q-Channel, – Line.
Source or sink current through this pin to trim DC offset.
Control Pins
MIXENABLE (Pin E4):
Mixer Enable Pin. If MIXENABLE =
high (the input voltage is higher than 2.0V), the mixer is
enabled. If MIXENABLE = low (the input voltage is less than
1.0V), it is disabled. If the enable function is not needed,
then this pin should be tied to V
CC1
.
AMP1ENABLE (Pins D5, L5):
First Amplifier Enable Pin.
AMP1ENABLE = high or floating results in normal (active)
operating mode for the first amplifier in each channel.
AMP1ENABLE = low (a minimum of 2.1V below V
CC2
),
results in the first amplifiers being disabled. If the enable
function is not needed, then this pin should be tied to V
CC2
.
AMP2ENABLE (Pins C10, L10):
Second Amplifier Enable
Pin. AMP2ENABLE = high or floating results in normal
(active) operating mode for the second amplifier in each
channel. AMP2ENABLE = low (a minimum of 0.45V below
V
CC3
), results in the second amplifiers being disabled. If
the enable function is not needed, then this pin should
be tied to V
CC3
.
ADCSHDNQ (Pin J12):
Q-Channel ADC Shutdown Mode
Selection Pin. Connecting ADCSHDNQ to GND and
OEQ
to
GND results in normal operation with the outputs enabled.
Connecting ADCSHDNQ to GND and
OEQ
to V
DD
results
in normal operation with the outputs at high impedance.
Connecting ADCSHDNQ to V
DD
and
OEQ
to GND results in
nap mode with the outputs at high impedance. Connecting
ADCSHDNQ to V
DD
and
OEQ
to V
DD
results in sleep mode
with the outputs at high impedance.
ADCSHDNI (Pin D12):
I-Channel ADC Shutdown Mode
Selection Pin. Connecting ADCSHDNI to GND and
OEI
to
GND results in normal operation with the outputs enabled.
Connecting ADCSHDNI to GND and
OEI
to V
DD
results in
normal operation with the outputs at high impedance.
pin FuncTions
