LTM9004
19
9004fa
CLK
5pF-30pF
ETC1-1T
0.1µF
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
9004 F09
LTM9004
V
DD
2
For more information
www.linear.com/LTM9004
Figure 8 and Figure 9 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the ADC is 125Msps.
The lower limit of the sample rate is determined by the
droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTM9004 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3V
DD
or 2/3V
DD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
applicaTions inForMaTion
Figure 8. CLK Driver Using an LVDS or PECL to
CMOS Converter
Figure 9. LVDS or PECL CLK Drive Using a Transformer
CLK
100Ω
0.1µF
4.7µF
FERRITE
BEAD
CLEAN
SUPPLY
9004 F08
LTM9004
