LTC3558
26
3558f
The output fi lter zero is given by:
f
R
C
Hz
FILTER ZERO
ESR
OUT
_
• •
•
=
1
2
π
where R
ESR
is the capacitor equivalent series resistance.
A troublesome feature in boost mode is the right-half
plane zero (RHP), and is given by:
f
PV
I
L V
Hz
RHPZ
IN
OUT
OUT
=
2
2
2
2 • •
• •
π
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network, as shown in Figure
10, can be incorporated to stabilize the loop, but at the
cost of reduced bandwidth and slower transient response.
To ensure proper phase margin, the loop requires to be
crossed over a decade before the LC double pole.
The unity-gain frequency of the error amplifi er with the
Type I compensation is given by:
f
R
C
Hz
UG
P
• •
•
=
1
2
1
1
π
Buck-Boost Switching Regulator Output Voltage
Programming
The buck-boost switching regulator can be programmed
for output voltages greater than 2.75V and less than 5.45V.
To program the output voltage, a resistor divider is con-
nected between V
OUT2
and the feedback node (FB2) as
shown in Figure 9. The output voltage is given by V
OUT2
= 0.8(1 + R1/R2).
APPLICATIONS INFORMATION
Figure 10. Error Amplifi er with Type I Compensation
R1
R2
3558 F10
0.8V
FB2
V
C2
C
P1
V
OUT2
–
+
ERROR
AMP
Figure 9. Programming the Buck-Boost Output Voltage Requires
a Resistor Divider Connected Between V
OUT2
and FB2
LTC3558
FB2
V
OUT2
R2
R1
3558 F09
Closing the Feedback Loop
The LTC3558 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck-boost), but is usually no greater than 20. The
output fi lter exhibits a double pole response given by:
f
L C
Hz
FILTER POLE
OUT
_
• •
•
=
1
2
π
where C
OUT
is the output fi lter capacitor.
