LTC3350
11
3350fc
For more information
www.linear.com/LTC3350
pin FuncTions
current around the capacitor to provide balancing and
prevent overvoltage. If not used this pin should be shorted
to CAP1. The voltage between this pin and CAP1 is digitized
and can be read in the meas_vcap2 register.
CAP3 (Pin 15):
Third Supercapacitor Pin. The top plate of
the third supercapacitor and the bottom plate of the fourth
supercapacitor are connected to this pin through a shunt
resistor. CAP3 and CAP2 are used to measure the voltage
across the third supercapacitor and to shunt current around
the capacitor to provide balancing and prevent overvoltage.
If not used this pin should be shorted to CAP2. The voltage
between this pin and CAP2 is digitized and can be read in
the meas_vcap3 register.
CAP4 (Pin 16):
Fourth Supercapacitor Pin. The top plate of
the fourth supercapacitor is connected to this pin through
a shunt resistor. CAP4 and CAP3 are used to measure
the voltage on the capacitor and to shunt current around
the supercapacitor to provide balancing and prevent
overvoltage. If not used this pin should be shorted to CAP3.
The voltage between this pin and CAP3 is digitized and
can be read in the meas_vcap4 register. The capacitance
test current set by the ITST pin is pulled from this pin.
CFP (Pin 17):
VCAPP5 Charge Pump Flying Capacitor
Positive Terminal. Place a 0.1μF between CFP and CFN.
CFN (Pin 18):
VCAPP5 Charge Pump Flying Capacitor
Negative Terminal. Place a 0.1μF between CFP and CFN.
VCAPP5 (Pin 19):
Charge Pump Output. The internal
charge pump drives this pin to VCAP + INTV
CC
which is
used as the high side rail for the OUTFET gate drive and
charge current sense amplifier. Connect a 0.1μF capacitor
from VCAPP5 to VCAP.
OUTFET (Pin 20):
Output Ideal Diode Gate Drive Out-
put. This pin controls the gate of an external N-channel
MOSFET used as an ideal diode between V
OUT
and V
CAP
.
The gate drive receives power from the internal charge
pump output VCAPP5. The source of the N-channel
MOSFET should be connected to VCAP and the drain should
be connected to VOUTSN. If the output ideal diode MOSFET
is not used, OUTFET should be left floating.
VCAP (Pin 21):
Supercapacitor Stack Voltage and Charge
Current Sense Amplifier Negative Input. Connect this pin
to the top of the supercapacitor stack. The voltage at this
pin is digitized and can be read in the meas_vcap register.
ICAP (Pin 22):
Charge Current Sense Amplifier Positive
Input. The ICAP and VCAP pins measure the voltage across
the sense resistor, R
SNSC
, to provide instantaneous cur-
rent signals for the control loops and ESR measurement
system. The maximum charge current is 32mV/R
SNSC
.
VCC2P5 (Pin 23):
Internal 2.5V Regulator Output. This
regulator provides power to the internal logic circuitry.
Decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
SW (Pin 24):
Switch Node Connection to the Inductor.
The negative terminal of the boot-strap capacitor, C
B
, is
connected to this pin. The voltage on this pin is also used
as the source reference for the top side N-channel MOS-
FET gate drive. In step-down mode, the voltage swing on
this pin is from a diode (external) forward voltage below
ground to V
OUT
. In step-up mode the voltage swing is from
ground to a diode forward voltage above V
OUT
.
TGATE (Pin 25):
Top Gate Driver Output. This pin is the
output of a floating gate driver for the top external N-channel
MOSFET. The voltage swing at this pin is ground to V
OUT
+ DRV
CC
.
BST (Pin 26):
TGATE Driver Supply Input. The positive
terminal of the boot-strap capacitor, C
B
, is connected to
this pin. This pin swings from a diode voltage drop below
DRV
CC
up to V
OUT
+ DRV
CC
.
BGATE (Pin 27):
Bottom Gate Driver Output. This pin
drives the bottom external N-channel MOSFET between
PGND and DRV
CC
.
DRV
CC
(Pin 28):
Power Rail for Bottom Gate Driver. Con-
nect to INTV
CC
or to an external supply. Decouple this pin
to ground with a minimum 2.2μF low ESR tantalum or
ceramic capacitor. Do not exceed 5.5V on this pin.
