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Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3.1.1 Features of AD6725
Complete Single-Chip Programmable Baseband Processor divided into several subsystems
MCU Control Processor Subsystem:
▪
32-bit ARM926EJ-S® MCU Control Processor
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208 MHz operation at 1.2V
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2 dedicated caches, 16kB each, for instructions and data
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4kB Instruction Tightly Coupled Memory (TCM)
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2-Mbit On-chip System SRAM
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Ciphering coprocessor for GPRS supporting GEA1 and GEA2 encryption algorithms
▪
Kasumi cipher coprocessor for GEA3 encryption
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Dedicated multichannel DMA controller
DSP Subsystem:
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16-bit fixed-point Blackfin® DSP Processor
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208 MHz operation at 1.
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Memory:
→
L1 program space: 64 kB SRAM and 16 kB configurable as instruction cache
or SRAM
→
L1 data space: Two banks of 16K bytes, each with 8K bytes of dedicated SRAM
and an additional 8K bytes that can be configured as either cache or SRAM
→
L2 space: 64KB SRAM
▪
Ciphering coprocessor (GEA1 and GEA2)
▪
Kasumi cipher coprocessor for GEA3 encryption
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Dedicated multichannel DMA controller
Peripherals Subsystem:
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Shared on-chip peripherals and off-chip interfaces:
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Support for Burst-mode, Page-mode, and NAND Flash memory
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Support for SRAM, SDRAM, and PSRAM (cellular RAM)
▪
Full-Speed USB 2.0 Dual-Role Interface with OTG (On-The-Go) Host Mode or
traditional Peripheral-only mode