IC201(MN103S63G) : ATAPI Interface, Write and DSP Signal Processor
Block Diagram
28
*1. Shaded blocks
: Work as system controller functions.
: New blocks for MN103S63G (MN103SEM0T63)
*2. The MN103SEM0T63 uses a 256-Kbyte SRAM as an instruction memory,
16-Kbyte data memory (8-Kbyte f/w and 8-Kbyte microcode), and 2-Mbit DRAM.
32-bit
CPU core
BCU
DRAMC
DMA
1-Mbit
DRAM
OnChip
Debug
Data memory
(6-Kbyte f/w)
(4-Kbyte microcode)
Instruction
memory
(128 Kbytes)
CGEN
MODE
WDT
16-bit
timerx6 f/w
timerx2 microcode
SYSTEM
I/F
INTC
General-
purpose
I/O
Serial
interface
HOST I/F
MPEG I/F
ECC
DMA I/F
ATAPI
General-purpose I/O bus
SERVO
IO
(Core1 IO)
SERVO
core
(Core2)
RAM
CIRC
DVD
-
ROM
Formatter
CD-
PRE
High-speed I/O bus
ANALOG
ATIP
BUEP
CDENC
Write
Strategy
DRAM I/F