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Chapter 6. BUFFER MEMORY AND I/O SIGNAL CONFIGURATON
6 - 4
2)
Output signals: PLC CPU module
à
High Speed Counter module
Signal
Contents
Remarks
P(N+1)0
Counter Preset Signal
P(N+1)1
Counter Set Signal
P(N+1)2
Counter operation enable signal
P(N+1)3
Increment/decrement count specification signal
P(N+1)4
Output enable signal
P(N+1)5
Home Latch enable signal
P(N+1)6
Coincidence rest signal
P(N+1)7
Carry/Borrow Reset Signal
Channel 0
P(N+1)8
Counter Preset Signal
P(N+1)9
Counter Set Signal
P(N+1)A
Counter operation enable signal
P(N+1)B
Increment/decrement count specification signal
P(N+1)C
Output enable signal
P(N+1)D
Home Latch enable signal
P(N+1)E
Coincidence rest signal
P(N+1)F
Carry/Borrow Reset Signal
Channel 1
※
‘N’ means the I/O word number of the High Speed Counter module.