19
Pin No.
Symbol
Type
Description
Ground pin for varipitch VCO circuitry.
Device Select. Cleared to zero indicates the MT1198 is master device.
Set to one indicates the MT1198 is slave device.
Device Active/Device 1 Present. This is a time-multiplexed signal which
indicates that a device is active, or that Device 1 is present. A 10K-ohm
pull-up resistor shall be connected to this signal externally.
Device Chip Select 1. This is the chip select signal from the host to select
the Control Block Registers.
Device Chip Select 0. This is the chip select signal from the host to select
the Command Block Registers.
Ground pin for internal digital circuitry.
Device Address. This is the 3-bit binary coded address provided by the
host to access an ATA register or data.
Passed Diagnostics. This signal is asserted by Device 1 to indicate to
Device 0 that it has completed diagnostics.
Power pin for internal digital circuitry.
Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16_indicates
to the host system that the 16-bit data port has been addressed and that
the device is prepared to send or receive a 16-bit data word. The MT1198
will always assert IOCS16_ when the host reads the ATAPI Data
Register.
Device interrupt. This signal is used to interrupt the host system. INTRQ
is driven only when the MT1198 is addressed, i.e.,
DRV101h.RW7=DRV16h.RW4. When not driven, INTRQ is in a high
impedance state.
DMA Acknowledge. This signal shall be used by the host in response to
DMARQ to acknowledge that it is ready for DMA transfers.
I/O Channel Ready. This signal is negated (pulled low) during PIO to
extend the host transfer cycle of any host register access (Read or Write)
when the MT1198 is not ready to respond to a data transfer request.
When IORDY is not negated, it is in a high impedance state. In Ultra
DMA transfers, the signal becomes either DDMARDY_(Device Ultra
DMA Ready) that is asserted by the MT1198 to indicate to the host that it
is ready to receive data, or DSTROBE (Device Ultra DMA Data Strobe)
whose rising edge and falling edge latch the data from DD0-DD15 into
the host.
Device I/O Read. This is the ATA read strobe signal. In PIO or multiword-
DMA the falling edge of DIOR_ enables data from the MT1198 onto the
host data bus, DD0-DD7 or DD0-DD15. The rising edge of DIOR_ then
latches the data at the host. During Ultra DMA transfers the signal
becomed either HDMARDY_ (Host Ultra DMA Ready), which is asserted
by the host to indicate to the MT1198 that host is ready to receive data,
or HSTROBE (Host Ultra DMA Data Strobe), whose rising edge and
falling edge latch the data from DD0-DD15 into the MT1198.
Device I/O Write. This is the ATA write strobe signal. In PIO or multiword-
DMA the rising edge of DIOW_ latches data from the host data bus,
DD0-DD7 or DD0-DD15, into the ATA registers or the ATAPI Packet FIFO
of the MT1198. In Ultra DMA transfers the signal becomes STOP (Stop
Ultra DMA Data Transfer), which is negated by the host before data can
be transferred by an Ultra DMA burst, and asserted by the host when it
want to terminate an Ultra DMA burst.
VPVSS
DEVSEL
DASP_
CS3FX_
CS1FX_
DGND
DA[2:0]
PDIAG_
DVDD
IOCS16_
INTRQ
DMACK_
IORDY
DOIR_
DIOW_
98
99
100
101
102
103
104,105,107
106
108
109
110
111
112
113
114
Ground
TTL Input
50K pull_up
TTL I/O
50K pull_up
TTL Input, SMT
50K pull_up
TTL Input, SMT
50K pull_up
Ground
TTL Input, SMT
50K pull_up
TTL Input,
50K pull_up
Power(5V)
TTL Output,
Open drain
TTL I/O
Slew rate
TTl Input, SMT
50K pull_up
TTL Output
Slew rate
TTL Input, SMT
50K pull_up
TTL Input, SMT
50K pull_up
Host Interface
