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LGE Internal Use Only
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. Technical Brief
BL20
19/53
3.8 SUB SYSTEM
3.8.1 KEY PAD
QSC62x0 devices provide a keypad interface that supports five sense lines, or columns, and (typically) five
keypad rows (though more can be software defined). The columns are a set of five QSC pins that are used for
sensing (KEYSENSE_xN); another set of pins are connected to the keypad’s rows and are used for driving
(KYPD_x). The sensed columns reveal when any keypad button is pressed, and then the rows are driven
sequentially to determine precisely which keypad button was pressed.
3.8.2 External memory interface
The QSC62x0 device has two external bus interface (EBI) ports: EBI1 and EBI2.
EBI1 supports high-speed synchronous dynamic devices. Its memory controller supports the new mobile DDR
SDRAM memories with its higher bandwidth and ability to run at high clock frequencies. This interface supports
the high-bandwidth, high-density, and low-latency requirements of the QSC’s advanced on-chip capabilities such
as the ARM9 processor, highperformance graphics, and video applications.
EBI2 is the slower speed interface intended to support memory devices such as NAND flash and asynchronous
SRAM, peripheral devices such as LCDs, and the UBM receiver for multicast or broadcast reception (QSC6270 only).
In addition, EBI2 is required to support a synchronous-burst AAD NOR flash to enable a NOR/DDR SDRAM memory
configuration because the simultaneous mode (NOR, SDRAM) is not supported on the EBI1 bus.
EBI1 Features
EBI1 is a high-performance external memory interface for the QSC62x0 digital block that supports DDR SDRAM
devices
Specifically, the following memory devices are supported on EBI1:
KEY_COL(2)
KEY_COL(1)
KEY_COL(0)
KEY_ROW(4)
KEY_ROW(3)
KEY_ROW(2)
KEY_ROW(1)
KEY_ROW(0)
KEY_ROW_1
KEY_ROW_2
KEY_ROW_3
KEY_ROW_4
KEY_COL_0
KEY_COL_1
KEY_ROW_0
KEY_COL_2