- 140 -
LGE Internal Use Only
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
6. Block Diagram
LG
E
In
te
rn
al
U
se
O
nl
y
C
ha
lle
ng
e
12
3
3.
S
ys
te
m
H
W
B
lo
ck
D
ia
gr
am
:
BB
B
lo
ck
Q
SC
62
70
MCP
(T
YA
00
0B
00
1
A
M
G
F
)
2
G
b
N
A
N
D
+
1
G
b
SD
RA
M
EB
I2
_
D
A
TA
[0
:1
5]
N
A
N
D
_C
S1
_N
EB
I2
_
AL
E
EB
I2
_
CL
E
EB
I2
_
O
E
_N
EB
I2
_
W
E
_N
N
A
N
D
_
RE
A
D
Y
RE
SO
U
T
_N
SD
RA
M
_
D
AT
A
[0
:3
1]
SD
RAM
_
AD
D
R
[0
:1
4]
SD
RAM
_
CL
K
SD
RAM
_CS
_N
(0)
SD
RAM
_
AD
V
_N
SD
RA
M
_
O
E
_N
SD
RA
M
_W
E
_N
SD
RA
M
_
CL
K
(0
)
SD
RA
M
_D
Q
M
[0
:3
]
VR
EG
_
M
SM
E
_1
.8
V
SI
M
CO
N
N
EC
TO
R
U
SI
M
_
D
A
TA
/
C
LK
/
R
ES
ET_
_N
VR
EG
_U
SIM
_2
.8
5V
5M
CA
M
ER
A
CA
M
_
M
CL
K
MICRO
SD
CONNECT
OR
LC
D
EB
I2
_
D
A
TA
[0
:1
5]
LC
D
_
M
AK
ER
_ID
EB
I2
_W
E_
N
/ EB
I2
_O
E_
N
LC
D
_
VS
YN
C
_
O
U
T
LC
D
_C
S
_N
LC
D
_A
D
S
LC
D
_
RES
ET
_N
LC
D
_
IF
_
M
O
D
E
LC
D
_
LD
O
_2
.8
V
Fr
om
L
D
O
A
U
D
IO
SU
B
SY
ST
EM
(M
A
X
98
77
A
EW
P
_
TG
45
)
SP
K
_R
/L
H
P
_R
/L
H
P
_
EA
R
_R
H
P
_
EA
R
_L
To
. M
M
I C
O
N.
SP
K
_
RCV
+/
-
RC
V
+/
-
To
.
Sp
ea
ke
r
I2
C
_
SC
L
I2
C
_
SD
A
FL
AS
H
D
riv
er
IC
FL
AS
H
_IN
H
FL
AS
H
_
SET
LC
D
CA
M
_
PC
LK
CA
M
_D
A
TA
[0
:9
]
CAM
_
H
SY
N
C
/
VS
YN
C
MEG
A
_C
AM
_
RESET
_N
I2
C
_
SCL
/SD
A
Fr
om
P
M
IC
LIN
M
O
T
_
PW
M
MOT
O
R
+
MOT
O
R
-
LIN
M
O
T
_
EN
TO
U
CH
_V
D
D
_2
.8
5
V
Fr
om
Q
SC
32
.7
68
KH
z
O
sc
ill
at
or
XT
A
L
_IN
XT
A
L
_
O
U
T
M
EG
A
_
CA
M
_
PW
D
N
SI
D
E
TO
U
CH
JT
A
G
JT
A
G
_T
D
I
JT
A
G
_T
CK
JT
A
G
_T
M
S
JT
A
G
_T
D
O
JT
A
G
_
TR
ST
_N
JT
A
G
_
RT
CK
SI
D
E
KE
Y
FR
O
M
S
ID
E
KEY
BLU
E
TOOTH
BT
_
PC
M
_
SY
N
C
BT
_P
CM
_IN
BT
_
PC
M
_
O
U
T
BT
_
PC
M
_
CL
K
BT
_
U
A
RT
_
TX
D
BT
_
U
A
RT
_
RX
D
BT
_
U
A
RT
_
CT
S
BT
_
U
A
RT
_
RT
S
BT
_
W
A
KEU
P
_M
SM
M
SM
_
W
A
KEU
P
_
BT
BT
_
RESET
_N
SL
EEP
_
CL
K
FM
_
AU
D
IO
_R
/L
CHAR
G
E
PU
M
P
(A
A
T
31
69
IF
O
-
T1
)
W
LE
D
_1
:5
M
LE
D
_O
U
T
+
VP
W
R
LC
D
B
L
CT
RL
I2
C
CO
M
M
.
FM
_
AN
T
Fr
om
M
M
I C
O
N
.
FM
R
A
D
IO
I2
C
_
SC
L
I2
C
_
SD
A
M
SM
E
_1
.8
V
M
IC
RO
SD
_
D
A
TA
[0
:3
]
M
IC
RO
SD
_
CM
D
/C
LK
M
IC
RO
_
D
ET
EC
T
_N
FM
_
RS
T
M
U
IC
_F
M
_A
U
D
IO
_
2C
_
SD
A
/
SC
L
M
U
IC
_IN
T
TO
U
CH
_V
D
D
_2
.8
5V
Fr
om
Q
SC
MA
IN
TO
U
CH
N
A
VI
KE
Y
FR
O
M
N
AV
I
+
VP
W
R
M
SM
P
_2
.6
V
Cr
ys
ta
l
26
M
H
Z
VG
A
_
LD
O
_2
.8
V
VG
A
_
LD
O
_1
.8
V
Fr
om
Q
SC
AF
_
LD
O
_2
.8
V
LC
D
_
LD
O
_1
.8
V
FL
AS
H
_
EN
+
VP
W
R
VR
EG
_M
IC
RO
SD
_3
.0
V
M
IC
MIC
_
BIAS
KEY
_
RO
W
(0
)
KEY
_
RO
W
(1
)
KEY
_
RO
W
(2
)
KEY
_
CO
L
(0
)
KEY
_
CO
L
(1
)
KEY
_
CO
L
(2
)
KEY
_
CO
L(
3)
KEY
_
CO
L(
4)
KE
Y
PA
D
19
.2
M
H
z
TC
XO
MMP
_
XT
AL
_
OU
T
VR
EG
_
TC
XO
_2
.8
5
V
H
A
LL
_IC
SL
ID
E
_
D
ETECT
VR
EG
_
M
SM
E
_1
.8
V
M
A
IN
_
LE
D
M
A
IN
_K
EY
_L
ED
_N
+
VP
W
R
SL
ID
E
_
LE
D
SL
ID
E
_K
E
Y
_L
ED
_N
+
VP
W
R
M
U
IC
U
SB
_
VB
U
S
U
SB
+/
-
U
SB
_I
D
5
PI
N
MICR
O
M
M
I
CO
N
N
.
U
SB
D
+/
-
U
A
RT
1
_
RX
/T
X
H
P
_R
/L
M
IC
_2
P
+
VP
W
R
Q
SC
G
PI
O
I2
C
_
SD
A
(G
PIO
39
_P
5_
1.
8V
)
I2
C
_
SC
L
(G
PIO
40
_P
5_
1.
8V
)
M
EG
A
/V
G
A
CA
M
ER
A
MU
IC_
FM_
A
U
D
IO_
I2
C
_
SD
A
(GP
IO
49
_P
1_
1.
8V
)
_
SC
L
(G
PIO
50
_P
1_
1.
8V
)
M
U
IC
/A
U
D
IO
FM
R
A
D
IO
M
U
IC
_
IN
T(
G
PI
O
10
_P
1_
1.
8V
)
I2
C
_
SD
A
(G
PIO
70
_P
3_
2.
85
V)
I2
C
_
SC
L
(G
PIO
71
_P
3_
2.
85
V
)
M
A
IN
T
O
U
CH
SI
D
E
TO
U
CH
M
A
IN
_
TO
U
CH
_
IN
T(
M
PP
2_
2.
85
V
)
SI
D
E
_
TO
U
CH
_
IN
T(
M
PP
4_
2.
85
V
)
Q
SC
M
PP
CA
M
_
M
U
IC
_F
M
_A
U
D
IO
_I
2C
CA
M
_
CA
M
_
I2
C
_
SD
A
(G
PIO
67
_P
3_
2.
85
V)
I2
C
_
SC
L
(G
PIO
68
_P
3
2.
85
V
)
M
A
IN
_T
O
U
CH
_
M
A
IN
_T
O
U
CH
_
SI
D
E_
TO
U
CH
_
SI
D
E_
TO
U
CH
_
LI
N
M
O
TO
R
D
RI
VE
R
To
.
MOT
O
R
LIN
M
O
T
_L
D
O
_3
.0
V
I2
C
_
SD
A
I2
C
_
SC
L
MA
IN
_
TOU
CH
_
INT
I2
C
_
SD
A
I2
C
_
SC
L
M
A
IN
_T
O
U
CH
_
M
A
IN
_T
O
U
CH
_
SI
D
E_
TO
U
CH
_
SI
D
E_
TO
U
CH
_
SI
D
E
_
TO
U
CH
_
IN
T
M
U
IC
_F
M
_A
U
D
IO
_
BT
_
REG
_
O
N
M
SM
E
_1
.8
V
M
SM
P
_2
.6
V
BT
_
AN
T
Fr
om
B
T
ch
ip
A
N
T.
3. System HW Block Diagram : BB Block