3. TECHNICAL BRIEF
- 34 -
Figure 3-17 AD6537B POWER MODE LOGIC
THERM
AD6537B
DDLO
UVLO
CHGDET
VBAT
KEYON
DBBON
VRTC
VEXT
VCXOEN
Thermal
Shutdown
POWERMODE
Enable
Mode
Enable
Mode
Enable
Mode
Enable
Mode
Enable
Mode
Digital Core
LDO Regulator
Memory Interface
LDO Regulator
LDO Regulator
External Interface
LDO Regulator
SIM Interface
LDO Regulator
VCXO
VEXT mode
Control Bit
VSIMEn
Control Bit
VMEM Comparator
VCORE Comparator
VEXT Comparator
VMEM
VMEMCP
VCORECP
VCORE
VEXT
VEXTCP
high: VEXT > 2.6V
high:VMEM > 2.6V or 1.6V
low: VMEM < 2.6V or 1.6V
high:VCORE > 1.6V
low: VCORE < 1.6V
low: VEXT < 2.6V
VCORE
VMEM
VEXT
VSIM
VVCXO
2. LDO Block
1. There are 8 LDOsin the AD6537B.
-VCORE : supplies Digital basebandProcessor core and AD6537B digital core
(1.8V, 80mA)
-VMEM : supplies external memory and the interface to the external memory on the
digital baseband processor (1,8V or 2.8V, 150mA)
-VEXT : supplies Radio digital interface and high voltage interface (2.8V, 170mA)
-VSIM : supplies the SIM interface circuitry on the digital processor and SIM card
(2.85V, 20mA)
-VRTC : supplies the Real-Time Clock module (1.8 V, 20 µA)
-VABB : supplies the analog portions of the AD6537B
-VMIC : supplies the microphone interface circuitry (2.5 V, 1 mA)-VVCXO : supplies the
voltage controlled crystal oscillator ( 2.75 V, 10 mA)
Summary of Contents for B2050
Page 7: ... 6 2 PERFORMANCE 2 PERFORMANCE 2 1 H W Features ...
Page 8: ... 7 2 PERFORMANCE ...
Page 9: ... 8 2 PERFORMANCE 2 2 Technical Specification ...
Page 10: ... 9 2 PERFORMANCE ...
Page 11: ... 10 2 PERFORMANCE ...
Page 12: ... 11 2 PERFORMANCE ...
Page 13: ... 12 2 PERFORMANCE ...
Page 57: ... 56 3 Checking Ant SW Mobile SW 4 TROUBLE SHOOTING ...
Page 67: ... 66 TEST POINT 4 6 LCD Trouble 4 TROUBLE SHOOTING ...
Page 70: ... 69 4 TROUBLE SHOOTING TEST POINT 4 7 Speaker Trouble ...
Page 77: ... 76 4 TROUBLE SHOOTING 4 10 KEY backlight Trouble TEST POINT ...
Page 92: ...5 DOWNLOAD AND CALIBRATION 91 5 2 Calibration ...
Page 93: ... 92 5 DOWNLOAD AND CALIBRATION ...
Page 97: ......
Page 103: ... 102 Figure 8 1 B2050 BOTTOM SIDE PCB LAYOUT 8 PCB LAYOUT ...
Page 104: ... 103 8 PCB LAYOUT Figure 8 1 B2050 TOP SIDE PCB LAYOUT ...
Page 105: ......
Page 113: ...10 STAND ALONE TEST 112 ...
Page 117: ......
Page 119: ......
Page 132: ... 131 ...
Page 133: ... 132 ...