LG B2050, Service Manual

Page: 28 / 133

3. TECHNICAL BRIEF
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Figure 3-10 AD6527 ARCHITECTURE
AD6527/AD6527B
AD6535
Audio Baseband
and Power
Management
DSP
SRAM
FLASH
MMI
USC
Peripheral
RF-Control
Subsystem
Subsystem
Subsystem
(ARM7TDMI
®
)
DMA and BUS
ARBITRATION
Serial Link
DSP BUS
RBUS IM
EBUS
PBUS
SBUS
MUC
The internal architecture of AD6527 is shown above Figure 3-10. AD6527 regroups three main subsys-
tems connected together through a dynamic and flexible communication bus network. It alsoincludes
onboard system RAM (SRAM) and interfaces with external Flash Memory, Basebandconverter functions,
and terminal functions like MMI, SIM and Universal System Connector (USC).The Digital Signal
Processing (DSP) subsystem primarily hosts all the speech processing, channel equalization and channel
codec functions. The code used to implement such functions can be storedin external Flash Memory and
dynamically downloaded on demand into the DSP’sprogram RAM andInstruction Cache.
The micro-controller subsystem supports all the GSM terminal software, including the layer 1, 2 and 3of
the GSM protocol stack, the MMI, and applications software such as data services, test and mainte-
nance. It is tightly associated with on-chip system SRAM and also includes boot ROM memory with a
small dedicated routine to facilitate the initialization of the external Flash Memory via code download
using the on-chip serial interface to the external Flash Memory interface.The peripheral subsystem is
composed of system peripherals such as interrupt controller, real timeclock, watch dog timer, power man-
agement and a timing and control module. It also includes peripheral interfaces to the terminal functions:
keyboard, battery supervision, radio and display. Boththe DSP and the MCU can access the peripheral
subsystem via the peripheral bus (PBUS).For program and data storage, both the MCU subsystem and
the DSPsubsystem can access the onchip system SRAM and external memory such Flash Memory. The
access to the SRAM module ismade through the RAM Bus (RBUS) under the control of the bus arbitra-
tion logic. Similarly, access tothe Flash Memory is through the parallel External Bus (EBUS).