3. TECHNICAL BRIEF
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1. Power up sequence logic
1. The AD6537B controls power on sequence
2. Power on sequence
-If a battery is inserted, the battery powers the 8 LDOs.
-Then if PWRONKEY is detected, the LDOsoutput turn on.
-REFOUT is also enabled
-Reset is generated and send to the AD6527
Figure 3-16 AD6537B POWER MANAGEMENT SECTION
AD6537B
Control
Serial
Port
CSFS
CSDI
CSDO
1.8V, 80mA
VCORE
1.8 or 2.8V, 150mA
VMEM
VEXT
2.8V, 170mA
VSIM
1.8 or 2.85V, 20mA
1.8V, 20 A
VRTC
VCXOEN
DBBON
RESET
VABB
VMIC
2.5V, 1mA
VVCXO
2.75V, 10mA
VCHG
GATEDRIVE
BATTYPE
ISENSE
KEYON
KEYOUT
Battery
Charer
Didital Core
LDO Regulator
Regulator
Control
Power-on
Reset Generator
Memory Interface
LDO Regulator
External Interface
LDO Regulator
SIM Interface
LDO Regulator
RTC
LDO Regulator
VCXO
LDO Regulator
Baseband Analog
LDO Regulator
Microphone
LDO Regulator
3.6.5 Power Management
Summary of Contents for B2050
Page 7: ... 6 2 PERFORMANCE 2 PERFORMANCE 2 1 H W Features ...
Page 8: ... 7 2 PERFORMANCE ...
Page 9: ... 8 2 PERFORMANCE 2 2 Technical Specification ...
Page 10: ... 9 2 PERFORMANCE ...
Page 11: ... 10 2 PERFORMANCE ...
Page 12: ... 11 2 PERFORMANCE ...
Page 13: ... 12 2 PERFORMANCE ...
Page 57: ... 56 3 Checking Ant SW Mobile SW 4 TROUBLE SHOOTING ...
Page 67: ... 66 TEST POINT 4 6 LCD Trouble 4 TROUBLE SHOOTING ...
Page 70: ... 69 4 TROUBLE SHOOTING TEST POINT 4 7 Speaker Trouble ...
Page 77: ... 76 4 TROUBLE SHOOTING 4 10 KEY backlight Trouble TEST POINT ...
Page 92: ...5 DOWNLOAD AND CALIBRATION 91 5 2 Calibration ...
Page 93: ... 92 5 DOWNLOAD AND CALIBRATION ...
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Page 103: ... 102 Figure 8 1 B2050 BOTTOM SIDE PCB LAYOUT 8 PCB LAYOUT ...
Page 104: ... 103 8 PCB LAYOUT Figure 8 1 B2050 TOP SIDE PCB LAYOUT ...
Page 105: ......
Page 113: ...10 STAND ALONE TEST 112 ...
Page 117: ......
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