URSA9 Block Diagram
URSA9
LGE7410
L_DIM_EN
I2C_SCL1/SDA1
1Gb x 4 (1600)
DDR3
16x4
Vx1 8Lane(12Lane_5K) 41P
Vx1 8Lane 51P
U14
4K@60p Vx1 8 Lane Video
1080p / 2160p Vx1 4 Lane OSD
[GPIO[15]]
URSA9_CONNECT
[GPIO[3]]
[GPIO[16]/[17]]
Vx1_LOCKn_O/V
[LOCKN_D/Q]
H1
3
LOCKn_IN/ HTPDn_IN
[VX1T_LOCKN]
[VX1T_HTDPN]
Panel
3840x2160@120
p
Serial
Flash(4MB)
SPI_CZ
SPI_D
O
SPI_CK
SPI_DI
XIN_URSA
XO_URSA
URSA_RESET_SOC
(H13D GPIO[26])
[RESET]
[I2CS_SDA/SCL]
I2CS_SDA/SCL
TCON_I2C_EN
[INT_R21/GPIO[41]]
(URSA Debug)
UART2_RX
UART2_TX
GPIO[1]/[0]
[SPI4_DI/DIM9/GPIO53]
[SPI4_DI/DIM9/GPIO53]
FLASH_WP_URSA
GPIO[25]
DIM5/GPIO[37]
DIM6/GPIO[38]
DIM7/GPIO[39]
URSA_BIT0/1/2
BIT[2/1/0]
UD_V x 1 Lane
0/0/0
4K@120P _16Lanes
0/0/1
4K@60P _ 8Lanes
0/1/0
5K@120P _ 20Lanes
[Tx_U14_0N/0P~7N/7P]
[Tx_U14_8N/8P~11N/11P]
[TXDAN0/P0~N7/P7_L]
[TXDBN0/P0~N7/P7_L]
X-tal
24MHz
[SPI4_CK/DIM8/GPIO52]
3D_EN
[GPIO[4/5]]
Data_Format_0/1
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 77EG9700
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